JP5381280B2 - 光結合装置 - Google Patents
光結合装置 Download PDFInfo
- Publication number
- JP5381280B2 JP5381280B2 JP2009105552A JP2009105552A JP5381280B2 JP 5381280 B2 JP5381280 B2 JP 5381280B2 JP 2009105552 A JP2009105552 A JP 2009105552A JP 2009105552 A JP2009105552 A JP 2009105552A JP 5381280 B2 JP5381280 B2 JP 5381280B2
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- JP
- Japan
- Prior art keywords
- light receiving
- light
- conversion element
- coupling device
- optical coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Description
光結合装置の2つのタイプを図1及び図2に示す。図1は対向型の光結合装置の断面図であり、図2は並置型の光結合装置の断面図である。
つぎに、光結合装置の光起電力を高めるために一般に用いられている構造について説明する。光結合装置の受光素子は、通常、単一の受光セルで形成することは少なく、複数個の受光セルを並べて受光領域を形成し、各受光セルを直列接続している。このような構造によれば、全体としての起電力は、個々の受光セルの起電力の総和となるので、大きな光起電力を得ることができる。
並置型の光結合装置において受光セルの受光量を均一化する方法としては、反射面形状に工夫をこらしたものが種々提案されている。例えば、特許文献2に開示された光結合半導体装置では、透光性樹脂の上面に断面三角形状の突起部を設けている。また、特許文献3に開示された光結合装置では、透光性樹脂の表面を楕円形状に成形してその周面に反射膜を形成し、その楕円焦点に発光素子と受光素子を配置している。特許文献4に開示された光結合装置では、透光性樹脂の上面にフレネルレンズ状のレンズ面を形成している。
まず、実施形態1の光結合装置31の構造を説明する。図4は、実施形態1による光結合装置31の構造を示す断面図である。図5は、光結合装置31の内部においてリードフレーム32、33の素子実装部32a、33aに実装された発光素子34(第1の変換素子)と受光素子35(第2の変換素子)を示す平面図である。
つぎに、光結合装置31の製造プロセスを説明する。
(1) まず、電気伝導性と熱伝導性に優れた材質(たとえば銅系の材質。あるいは鉄系の材質や42アロイでもよい。)のフープ材をパンチングまたはエッチングすることにより、所望形状のリードフレーム32、33、40〜42などを形成する。ついで、各リードフレーム32、33、40〜42のインナーリードに、ワイヤボンド性を良好にするようなメッキ処理(たとえばCu下地にAgメッキしたもの。あるいは、Ni/Pd下地にAuメッキしたものでもよい。)を施した後、リードフレーム32、33にそれぞれ、導電性接着剤(たとえばAgペーストすなわちAg粒子を含んだエポキシ樹脂でもよい。)などで発光素子34、受光素子35をダイボンダ等の装置で搭載する。導電性接着剤の場合は、100〜150℃程度のオーブンで熱硬化させる。受光素子35は、共晶結合でリードフレーム33に接合(搭載)される場合もある。
本実施形態の光結合装置31によれば、受光セル46を直列に接続しているので、光起電力を大きくできることを説明したが、さらに受光素子35に発生する光電流も大きくできることを比較例2と比較しながら説明する。図9(a)及び図10(a)は比較例2の光結合装置101の要部を示す概略断面図であり、図9(b)及び図10(b)は光結合装置101の受光素子105における光照射強度の分布を表した図である。なお、図9(b)及び図10(b)における破線は、光信号による光照射強度の分布を表しており、太い破線eは光照射強度の高い領域を示し、細い破線gは光照射強度の低い領域を示し、中間の太さの破線fは中間の光強度の領域を表している。
図14は本発明の実施形態2による光結合装置51の要部の構造を示す平面図である。実施形態1の光結合装置31では、平行に配列された各受光セル46は等しい幅を有していたが、この光結合装置51では、中央部の受光セル46の幅を狭くし、端の受光セル46ほど幅が広くなるようにしている。他の構成については、実施形態1と同様であるので、説明は省略する。
図15は、本発明の実施形態5による光結合装置52を示す断面図である。この光結合装置52でも、発光素子34と受光素子35は、それぞれ素子実装部32aと34aにおいて同じ向きの面に実装されているので並置型の光結合装置となっている。さらに、この光結合装置52では、発光素子34を実装した素子実装部32aが受光素子35を実装した素子実装部33aよりも高くなっている。
図17は本発明の実施形態4によるMOSドライバ61の回路構成を示す平面図である。このMOSドライバ61は、実施形態1の光結合装置31において、受光素子35と並列に制御回路62を接続したものである。制御回路62は光結合装置31に外付けされるのでなく、発光素子34や受光素子35とともに封止樹脂37内に封止されている。
図18は本発明の実施形態5による半導体リレー63の要部の構造を示す平面図である。この半導体リレー63は、前記MOSドライバ61において、受光素子35の一端(アノード側)に2つのMOSFET64、65のゲート電極を接続し、また受光素子35の他端(カソード側)に各MOSFET64、65のソース電極を接続し、MOSFET64、65のドレイン電極を半導体リレー63の出力端子としたものである。MOSFET64、65はMOSドライバ61に外付けされるのでなく、発光素子34や受光素子35、制御回路62とともに封止樹脂37内に封止されている。
32、33、40、41、42 リードフレーム
32a、33a 素子実装部
34 発光素子
35 受光素子
36 透光性樹脂
37 封止樹脂
43、44 ワイヤボンドパッド
46 受光セル
48 光反射樹脂層
61 MOSドライバ
63 半導体リレー
Claims (4)
- 電気信号を光信号に変換する第1の変換素子と光信号を電気信号に変換する第2の変換素子をそれぞれの端子板の素子実装部において同じ向きの面に実装し、前記第1の変換素子と前記第2の変換素子を覆うようにして光反射曲面を形成し、前記第1の変換素子から発した光信号を前記光反射曲面で反射させることによって前記第1の変換素子と前記第2の変換素子を光学的に結合させた光結合装置において、
前記第2の変換素子は、電気的に直列に接続され、かつ、互いに平行に配列された一方向に長い複数個の受光セルを有し、
前記第1の変換素子は、前記第2の変換素子の輪郭に接するように定めた、前記受光セルの長さ方向と平行な2本の接線に挟まれた領域内に配置されていることを特徴とする光結合装置。 - 互いに平行に配列された前記受光セルのうち、中央部に位置する受光セルの幅が狭く、端に位置する受光セルの幅が広くなっていることを特徴とする、請求項1に記載の光結合装置。
- 電気信号を光信号に変換する第1の変換素子と光信号を電気信号に変換する第2の変換素子をそれぞれの端子板の素子実装部において同じ向きの面に実装し、前記第1の変換素子と前記第2の変換素子を覆うようにして光反射曲面を形成し、前記第1の変換素子から発した光信号を前記光反射曲面で反射させることによって前記第1の変換素子と前記第2の変換素子を光学的に結合させた光結合装置において、
前記第2の変換素子は、電気的に直列に接続され、かつ、互いに平行に配列された一方向に長い複数個の受光セルを有し、
前記第1の変換素子は、前記第2の変換素子の輪郭に接するように定めた、前記受光セルの長さ方向と平行な2本の接線に挟まれた領域内に配置され、
MOSFETを駆動するための制御回路が、前記第2の変換素子と並列に接続されたことを特徴とするMOSドライバ。 - 電気信号を光信号に変換する第1の変換素子と光信号を電気信号に変換する第2の変換素子をそれぞれの端子板の素子実装部において同じ向きの面に実装し、前記第1の変換素子と前記第2の変換素子を覆うようにして光反射曲面を形成し、前記第1の変換素子から発した光信号を前記光反射曲面で反射させることによって前記第1の変換素子と前記第2の変換素子を光学的に結合させた光結合装置において、
前記第2の変換素子は、電気的に直列に接続され、かつ、互いに平行に配列された一方向に長い複数個の受光セルを有し、
前記第1の変換素子は、前記第2の変換素子の輪郭に接するように定めた、前記受光セルの長さ方向と平行な2本の接線に挟まれた領域内に配置され、
MOSFETを駆動するための制御回路が、前記第2の変換素子と並列に接続され、
前記接続回路の両端にそれぞれMOSFETが接続されたことを特徴とする半導体リレー。
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