JP5363879B2 - ドライバ回路 - Google Patents

ドライバ回路 Download PDF

Info

Publication number
JP5363879B2
JP5363879B2 JP2009133941A JP2009133941A JP5363879B2 JP 5363879 B2 JP5363879 B2 JP 5363879B2 JP 2009133941 A JP2009133941 A JP 2009133941A JP 2009133941 A JP2009133941 A JP 2009133941A JP 5363879 B2 JP5363879 B2 JP 5363879B2
Authority
JP
Japan
Prior art keywords
power supply
driver
overvoltage protection
breakdown voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009133941A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010283499A5 (enExample
JP2010283499A (ja
Inventor
哲 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009133941A priority Critical patent/JP5363879B2/ja
Priority to US12/662,770 priority patent/US7973585B2/en
Publication of JP2010283499A publication Critical patent/JP2010283499A/ja
Publication of JP2010283499A5 publication Critical patent/JP2010283499A5/ja
Application granted granted Critical
Publication of JP5363879B2 publication Critical patent/JP5363879B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP2009133941A 2009-06-03 2009-06-03 ドライバ回路 Expired - Fee Related JP5363879B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009133941A JP5363879B2 (ja) 2009-06-03 2009-06-03 ドライバ回路
US12/662,770 US7973585B2 (en) 2009-06-03 2010-05-03 Driver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009133941A JP5363879B2 (ja) 2009-06-03 2009-06-03 ドライバ回路

Publications (3)

Publication Number Publication Date
JP2010283499A JP2010283499A (ja) 2010-12-16
JP2010283499A5 JP2010283499A5 (enExample) 2012-04-05
JP5363879B2 true JP5363879B2 (ja) 2013-12-11

Family

ID=43300294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009133941A Expired - Fee Related JP5363879B2 (ja) 2009-06-03 2009-06-03 ドライバ回路

Country Status (2)

Country Link
US (1) US7973585B2 (enExample)
JP (1) JP5363879B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091708A (ja) * 2009-10-23 2011-05-06 Elpida Memory Inc 半導体装置
KR101545803B1 (ko) * 2011-05-27 2015-08-19 로무 가부시키가이샤 부하 구동 장치 및 이를 사용한 전자 기기
JP5848679B2 (ja) * 2012-09-04 2016-01-27 ルネサスエレクトロニクス株式会社 差動出力回路および半導体装置
EP2713266B1 (en) * 2012-09-26 2017-02-01 Nxp B.V. Driver circuit
JP6429665B2 (ja) * 2015-02-19 2018-11-28 株式会社メガチップス Ｅｓｄ保護回路
KR102055315B1 (ko) * 2015-10-29 2019-12-13 위트리시티 코포레이션 무선 전력 시스템들용 제어기들
JP6042962B2 (ja) * 2015-11-27 2016-12-14 ルネサスエレクトロニクス株式会社 差動出力回路および半導体装置
US10298010B2 (en) * 2016-03-31 2019-05-21 Qualcomm Incorporated Electrostatic discharge (ESD) isolated input/output (I/O) circuits
US10360485B2 (en) 2016-08-29 2019-07-23 Integrated Device Technology, Inc. Circuits and systems for low power magnetic secure transmission
US12393113B2 (en) * 2020-05-06 2025-08-19 Kla Corporation Inter-step feedforward process control in the manufacture of semiconductor devices
US11863181B2 (en) * 2021-09-22 2024-01-02 Nxp Usa, Inc. Level-shifter

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249973A (ja) * 1994-03-14 1995-09-26 Toshiba Corp 電子機器
JPH08106345A (ja) * 1994-10-05 1996-04-23 Fujitsu Ltd 異電圧素子間インタフェース装置
US6429716B1 (en) * 1998-12-14 2002-08-06 Ati International Srl Pre-buffer voltage level shifting circuit and method
JP3344404B2 (ja) * 2000-03-14 2002-11-11 日本電気株式会社 ドライバ回路
JP3719671B2 (ja) * 2002-09-30 2005-11-24 松下電器産業株式会社 レベルシフタ回路
EP1783909B1 (en) * 2005-11-04 2008-05-07 Infineon Technologies AG Circuit arrangement with at least two semiconductor switches and a central overvoltage protection
JP4899563B2 (ja) * 2006-03-23 2012-03-21 富士通株式会社 電源制御回路
JP2007306042A (ja) * 2006-05-08 2007-11-22 Sony Corp レベル変換回路及びこれを用いた入出力装置

Also Published As

Publication number Publication date
US7973585B2 (en) 2011-07-05
JP2010283499A (ja) 2010-12-16
US20100308888A1 (en) 2010-12-09

Similar Documents

Publication Publication Date Title
JP5363879B2 (ja) ドライバ回路
US7295038B2 (en) Digital circuits having current mirrors and reduced leakage current
US6819142B2 (en) Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption
JP5313771B2 (ja) プリエンファシス機能を含む出力回路
KR20140084399A (ko) 디엠퍼시스 버퍼 회로
US7495483B2 (en) Input buffer for CMOS integrated circuits
US6366140B1 (en) High bandwidth clock buffer
JP2004350273A (ja) 電圧モード電流補助式プリエンファシスドライバ
JP4097149B2 (ja) 差動駆動回路およびそれを内蔵する電子機器
JP4552652B2 (ja) レベル変換回路
JP4568096B2 (ja) 入出力回路
JP4731333B2 (ja) レベルシフト回路
WO2006033638A1 (en) A digital voltage level shifter
KR100925034B1 (ko) 비동기 디지털 신호레벨 변환회로
US5767696A (en) Tri-state devices having exclusive gate output control
TWI822013B (zh) 包括位準移位器的半導體裝置以及減輕輸入訊號與輸出訊號之間的延遲的方法
CN110611497A (zh) 比较器以及振荡电路
EP1760889A2 (en) High speed input circuit
JP2012105135A (ja) 差動出力回路
JP4630782B2 (ja) レベルシフト回路
KR100713907B1 (ko) 반도체 장치의 라인 구동 회로
JP4602008B2 (ja) Ｃｍｏｓ出力バッファ回路
CN113179093A (zh) 一种cmos结构栅极驱动器
JP4232317B2 (ja) 差動増幅器
JP4981159B2 (ja) 入出力回路

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120220

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120220

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130301

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130402

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130530

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130618

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130802

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130827

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130906

R150 Certificate of patent or registration of utility model

Ref document number: 5363879

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees