JP5355363B2 - 半導体装置内蔵基板及びその製造方法 - Google Patents

半導体装置内蔵基板及びその製造方法 Download PDF

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Publication number
JP5355363B2
JP5355363B2 JP2009271902A JP2009271902A JP5355363B2 JP 5355363 B2 JP5355363 B2 JP 5355363B2 JP 2009271902 A JP2009271902 A JP 2009271902A JP 2009271902 A JP2009271902 A JP 2009271902A JP 5355363 B2 JP5355363 B2 JP 5355363B2
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Prior art keywords
insulating layer
semiconductor device
connection terminal
support
wiring pattern
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Japanese (ja)
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JP2011114304A (ja
JP2011114304A5 (enExample
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敏男 小林
孝治 山野
孝 栗原
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009271902A priority Critical patent/JP5355363B2/ja
Priority to US12/952,452 priority patent/US8232639B2/en
Publication of JP2011114304A publication Critical patent/JP2011114304A/ja
Publication of JP2011114304A5 publication Critical patent/JP2011114304A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2009271902A 2009-11-30 2009-11-30 半導体装置内蔵基板及びその製造方法 Active JP5355363B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009271902A JP5355363B2 (ja) 2009-11-30 2009-11-30 半導体装置内蔵基板及びその製造方法
US12/952,452 US8232639B2 (en) 2009-11-30 2010-11-23 Semiconductor-device mounted board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009271902A JP5355363B2 (ja) 2009-11-30 2009-11-30 半導体装置内蔵基板及びその製造方法

Publications (3)

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JP2011114304A JP2011114304A (ja) 2011-06-09
JP2011114304A5 JP2011114304A5 (enExample) 2012-10-18
JP5355363B2 true JP5355363B2 (ja) 2013-11-27

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US9070685B2 (en) * 2012-08-24 2015-06-30 Win Semiconductors Corp. Compound semiconductor integrated circuit
JP6500572B2 (ja) * 2015-04-14 2019-04-17 オムロン株式会社 回路構造体
JP7046639B2 (ja) * 2018-02-21 2022-04-04 新光電気工業株式会社 配線基板及びその製造方法
JP6658935B2 (ja) * 2019-03-01 2020-03-04 オムロン株式会社 回路構造体

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP2001185444A (ja) * 1999-12-24 2001-07-06 Kyocera Corp 薄膜電子部品
JP3652281B2 (ja) * 2000-06-30 2005-05-25 京セラ株式会社 薄膜電子部品および基板
JP3888267B2 (ja) * 2002-08-30 2007-02-28 カシオ計算機株式会社 半導体装置およびその製造方法
JP4056360B2 (ja) * 2002-11-08 2008-03-05 沖電気工業株式会社 半導体装置及びその製造方法
JP2005079431A (ja) * 2003-09-02 2005-03-24 Matsushita Electric Ind Co Ltd 半導体装置
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4441325B2 (ja) 2004-05-18 2010-03-31 新光電気工業株式会社 多層配線の形成方法および多層配線基板の製造方法
JP2006222164A (ja) 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007201254A (ja) * 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP5224845B2 (ja) * 2008-02-18 2013-07-03 新光電気工業株式会社 半導体装置の製造方法及び半導体装置

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US8232639B2 (en) 2012-07-31
JP2011114304A (ja) 2011-06-09

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