JP5348632B2 - デュアルモールドマルチチップパッケージシステムおよびその製造方法 - Google Patents

デュアルモールドマルチチップパッケージシステムおよびその製造方法 Download PDF

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Publication number
JP5348632B2
JP5348632B2 JP2007339497A JP2007339497A JP5348632B2 JP 5348632 B2 JP5348632 B2 JP 5348632B2 JP 2007339497 A JP2007339497 A JP 2007339497A JP 2007339497 A JP2007339497 A JP 2007339497A JP 5348632 B2 JP5348632 B2 JP 5348632B2
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integrated circuit
package system
circuit chip
lead
sealing material
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JP2008166816A5 (cg-RX-API-DMAC7.html
JP2008166816A (ja
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カンバンパティ・ラマクリシュナ
イル，クウォン・シム
セン，グアン・チョウ
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2007339497A 2006-12-30 2007-12-28 デュアルモールドマルチチップパッケージシステムおよびその製造方法 Active JP5348632B2 (ja)

Applications Claiming Priority (2)

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US11/618,806 US8178982B2 (en) 2006-12-30 2006-12-30 Dual molded multi-chip package system
US11/618,806 2006-12-30

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JP2008166816A5 JP2008166816A5 (cg-RX-API-DMAC7.html) 2011-02-17
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Publication number Publication date
US8178982B2 (en) 2012-05-15
KR20080063197A (ko) 2008-07-03
KR101521254B1 (ko) 2015-05-18
US8558399B2 (en) 2013-10-15
TW200836272A (en) 2008-09-01
JP2008166816A (ja) 2008-07-17
US20120193805A1 (en) 2012-08-02
US20080157402A1 (en) 2008-07-03
TWI441265B (zh) 2014-06-11

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