JP5341087B2 - 半導体デバイスの応力緩和 - Google Patents
半導体デバイスの応力緩和 Download PDFInfo
- Publication number
- JP5341087B2 JP5341087B2 JP2010520024A JP2010520024A JP5341087B2 JP 5341087 B2 JP5341087 B2 JP 5341087B2 JP 2010520024 A JP2010520024 A JP 2010520024A JP 2010520024 A JP2010520024 A JP 2010520024A JP 5341087 B2 JP5341087 B2 JP 5341087B2
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- JP
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- Prior art keywords
- crack prevention
- corner
- crack
- chip
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 18
- 230000002265 prevention Effects 0.000 claims description 120
- 239000002184 metal Substances 0.000 claims description 101
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 27
- 238000005520 cutting process Methods 0.000 description 19
- 230000032798 delamination Effects 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 238000009826 distribution Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241001272720 Medialuna californiensis Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
Claims (5)
- 活性領域およびチップ角部を有するチップと、
前記チップは、スクライブ領域をクラックストップの外側にさらに備え、前記クラックストップは前記活性領域を少なくとも部分的に取り囲むことと、
前記チップは、クラック阻止構造をさらに備え、前記クラック阻止構造の少なくとも一部分が前記チップの前記スクライブ領域に形成されることとを備えた半導体デバイスにおいて、前記チップは、
基板と、
前記基板を被覆し、かつ金属を含有する第1層と、
前記第1層を被覆し、かつ金属を含有する第2層と、
前記第2層を被覆し、かつ金属を含有する第3層とを備え、
前記クラック阻止構造は、
前記第1層に形成され、かつ前記チップ角部から第1距離に位置する第1外側角部を有する第1部分と、
前記第2層に形成され、かつ前記チップ角部から、前記第1距離よりも長い第2距離に位置する第2外側角部を有する第2部分と、
前記第3層に形成され、かつ前記チップ角部から、前記第2距離よりも長い第3距離に位置する第3外側角部を有する第3部分とを備え、
前記クラック阻止構造は前記スクライブ領域の第1の端縁から第2の端縁に延びるとともに、前記スクライブ領域の前記第1の端縁と第2の端縁の交点から離隔していることを特徴とする、半導体デバイス。 - エッジシールをさらに備え、前記エッジシールは前記活性領域を少なくとも部分的に取り囲む、請求項1に記載の半導体デバイス。
- 前記チップは、コーナー領域群と非コーナー領域とをさらに備え、前記非コーナー領域には、前記クラック阻止構造が配設されず、これらのコーナー領域のうちの少なくとも1つのコーナー領域は前記クラック阻止構造を備える、請求項1に記載の半導体デバイス。
- 前記クラック阻止構造は、前記第1層に形成される第4部分をさらに備え、前記第4部分は、前記チップ角部から第4距離に位置する第4外側角部を有し、前記第1距離は前記第4距離よりも長い、請求項1に記載の半導体デバイス。
- 前記クラック阻止構造は、
前記第2層に形成され、かつ前記チップ角部から第5距離に位置する第5外側角部を有する第5部分であって、前記第2距離が前記第5距離よりも長い、前記第5部分と、
前記第3層に形成され、かつ前記チップ角部から第6距離に位置する第6外側角部を有する第6部分であって、前記第3距離が前記第6距離よりも長い、前記第6部分とをさらに備える、請求項1に記載の半導体デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/835,680 | 2007-08-08 | ||
US11/835,680 US7960814B2 (en) | 2007-08-08 | 2007-08-08 | Stress relief of a semiconductor device |
PCT/US2008/068023 WO2009020713A1 (en) | 2007-08-08 | 2008-06-24 | Stress relief of a semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010536174A JP2010536174A (ja) | 2010-11-25 |
JP2010536174A5 JP2010536174A5 (ja) | 2011-08-11 |
JP5341087B2 true JP5341087B2 (ja) | 2013-11-13 |
Family
ID=40341625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010520024A Expired - Fee Related JP5341087B2 (ja) | 2007-08-08 | 2008-06-24 | 半導体デバイスの応力緩和 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7960814B2 (ja) |
JP (1) | JP5341087B2 (ja) |
KR (1) | KR101462063B1 (ja) |
CN (1) | CN101779286B (ja) |
TW (1) | TWI433222B (ja) |
WO (1) | WO2009020713A1 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8013425B2 (en) | 2008-05-13 | 2011-09-06 | United Microelectronics Corp. | Scribe line structure for wafer dicing and method of making the same |
US8912076B2 (en) * | 2008-11-05 | 2014-12-16 | Texas Instruments Incorporated | Crack deflector structure for improving semiconductor device robustness against saw-induced damage |
US8125053B2 (en) * | 2009-02-04 | 2012-02-28 | Texas Instruments Incorporated | Embedded scribe lane crack arrest structure for improved IC package reliability of plastic flip chip devices |
US8124448B2 (en) * | 2009-09-18 | 2012-02-28 | Advanced Micro Devices, Inc. | Semiconductor chip with crack deflection structure |
DE102010029528A1 (de) * | 2010-05-31 | 2011-12-01 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Halbleiterbauelement mit einer Chipumrandung mit gradueller Strukturdichte |
US8692392B2 (en) | 2010-10-05 | 2014-04-08 | Infineon Technologies Ag | Crack stop barrier and method of manufacturing thereof |
US20120286397A1 (en) * | 2011-05-13 | 2012-11-15 | Globalfoundries Inc. | Die Seal for Integrated Circuit Device |
US8940618B2 (en) * | 2012-03-13 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for cutting semiconductor wafers |
KR101984736B1 (ko) * | 2012-10-09 | 2019-06-03 | 삼성디스플레이 주식회사 | 플렉서블 디스플레이 장치용 어레이 기판 |
US8896102B2 (en) * | 2013-01-22 | 2014-11-25 | Freescale Semiconductor, Inc. | Die edge sealing structures and related fabrication methods |
US20140342471A1 (en) * | 2013-05-20 | 2014-11-20 | Varian Semiconductor Equipment Associates, Inc. | Variable Doping Of Solar Cells |
TWI467757B (zh) * | 2013-08-02 | 2015-01-01 | Chipbond Technology Corp | 半導體結構 |
CN106464162B (zh) | 2014-06-20 | 2019-02-19 | 通用电气公司 | 用于对多逆变器功率变换器的控制的装置及方法 |
US20160268166A1 (en) * | 2015-03-12 | 2016-09-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
KR102611982B1 (ko) | 2016-05-25 | 2023-12-08 | 삼성전자주식회사 | 반도체 장치 |
KR102633112B1 (ko) | 2016-08-05 | 2024-02-06 | 삼성전자주식회사 | 반도체 소자 |
CN109950208A (zh) * | 2017-12-21 | 2019-06-28 | 成都海存艾匹科技有限公司 | 适合划片且能避免裂痕的半导体晶粒 |
KR102599050B1 (ko) * | 2018-08-20 | 2023-11-06 | 삼성전자주식회사 | 반도체 칩의 제조 방법 |
JP7443097B2 (ja) | 2020-03-09 | 2024-03-05 | キオクシア株式会社 | 半導体ウェハおよび半導体チップ |
DE102022128335A1 (de) | 2022-10-26 | 2024-05-02 | Infineon Technologies Ag | Chip mit Rissleitstruktur kombiniert mit Rissstoppstruktur |
CN115376905B (zh) * | 2022-10-27 | 2023-01-31 | 山东中清智能科技股份有限公司 | 一种半导体晶片的切割工艺 |
CN116314041A (zh) * | 2023-05-24 | 2023-06-23 | 深圳和美精艺半导体科技股份有限公司 | 承载基板、应用其的封装结构及封装元件 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922326A (en) | 1988-07-18 | 1990-05-01 | Motorola, Inc. | Ceramic semiconductor package having crack arrestor patterns |
US4976814A (en) | 1988-07-18 | 1990-12-11 | Motorola, Inc. | Method of making a ceramic semiconductor package having crack arrestor patterns |
KR100447035B1 (ko) * | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치의 제조방법 |
US5858882A (en) | 1997-03-24 | 1999-01-12 | Vanguard International Semiconductor Corporation | In-situ low wafer temperature oxidized gas plasma surface treatment process |
US6709954B1 (en) | 2002-06-21 | 2004-03-23 | Advanced Micro Devices, Inc. | Scribe seal structure and method of manufacture |
US6972209B2 (en) | 2002-11-27 | 2005-12-06 | International Business Machines Corporation | Stacked via-stud with improved reliability in copper metallurgy |
US7098676B2 (en) | 2003-01-08 | 2006-08-29 | International Business Machines Corporation | Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor |
US7126225B2 (en) | 2003-04-15 | 2006-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling |
US20050026397A1 (en) | 2003-07-28 | 2005-02-03 | International Business Machines Corporation | Crack stop for low k dielectrics |
US7180187B2 (en) | 2004-06-22 | 2007-02-20 | International Business Machines Corporation | Interlayer connector for preventing delamination of semiconductor device |
US7129566B2 (en) * | 2004-06-30 | 2006-10-31 | Freescale Semiconductor, Inc. | Scribe street structure for backend interconnect semiconductor wafer integration |
US7223673B2 (en) | 2004-07-15 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device with crack prevention ring |
JP4636839B2 (ja) * | 2004-09-24 | 2011-02-23 | パナソニック株式会社 | 電子デバイス |
US7211500B2 (en) * | 2004-09-27 | 2007-05-01 | United Microelectronics Corp. | Pre-process before cutting a wafer and method of cutting a wafer |
JP2008066716A (ja) * | 2006-08-10 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP5175066B2 (ja) * | 2006-09-15 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2007
- 2007-08-08 US US11/835,680 patent/US7960814B2/en active Active
-
2008
- 2008-06-24 KR KR1020107001862A patent/KR101462063B1/ko active IP Right Grant
- 2008-06-24 JP JP2010520024A patent/JP5341087B2/ja not_active Expired - Fee Related
- 2008-06-24 CN CN2008801023319A patent/CN101779286B/zh active Active
- 2008-06-24 WO PCT/US2008/068023 patent/WO2009020713A1/en active Application Filing
- 2008-07-14 TW TW097126694A patent/TWI433222B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20100050489A (ko) | 2010-05-13 |
CN101779286A (zh) | 2010-07-14 |
US20090039470A1 (en) | 2009-02-12 |
WO2009020713A1 (en) | 2009-02-12 |
KR101462063B1 (ko) | 2014-11-17 |
US7960814B2 (en) | 2011-06-14 |
TW200913041A (en) | 2009-03-16 |
CN101779286B (zh) | 2012-01-11 |
TWI433222B (zh) | 2014-04-01 |
JP2010536174A (ja) | 2010-11-25 |
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