JP5315186B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5315186B2
JP5315186B2 JP2009217825A JP2009217825A JP5315186B2 JP 5315186 B2 JP5315186 B2 JP 5315186B2 JP 2009217825 A JP2009217825 A JP 2009217825A JP 2009217825 A JP2009217825 A JP 2009217825A JP 5315186 B2 JP5315186 B2 JP 5315186B2
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JP2011066340A5 (enExample
JP2011066340A (ja
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薫 横澤
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2009217825A priority Critical patent/JP5315186B2/ja
Priority to CN201010233605.7A priority patent/CN102024677B/zh
Priority to US12/848,784 priority patent/US8649896B2/en
Publication of JP2011066340A publication Critical patent/JP2011066340A/ja
Publication of JP2011066340A5 publication Critical patent/JP2011066340A5/ja
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Publication of JP5315186B2 publication Critical patent/JP5315186B2/ja
Priority to US14/167,008 priority patent/US9287142B2/en
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US12/848,784 US8649896B2 (en) 2009-09-18 2010-08-02 Manufacturing method of semiconductor device
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10290606B2 (en) * 2012-06-21 2019-05-14 Advanced Micro Devices, Inc. Interposer with identification system
JP5968705B2 (ja) 2012-07-13 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2014142729A (ja) * 2013-01-23 2014-08-07 Renesas Electronics Corp 半導体装置の製造方法
US8901715B1 (en) * 2013-07-05 2014-12-02 Infineon Technologies Ag Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking
JP6387256B2 (ja) 2014-07-07 2018-09-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2016103125A1 (en) * 2014-12-22 2016-06-30 Bombardier Inc. Reference system for online vision inspection
KR101661839B1 (ko) * 2015-01-05 2016-09-30 금오공과대학교 산학협력단 솔라셀 제조 공정 관리 방법
JP6103547B2 (ja) * 2015-01-09 2017-03-29 三菱電機株式会社 電子基板ユニット
JP6537277B2 (ja) * 2015-01-23 2019-07-03 キヤノン株式会社 インプリント装置、物品製造方法
JP6388547B2 (ja) * 2015-01-26 2018-09-12 株式会社ディスコ 切削装置
CN106332453A (zh) * 2015-06-16 2017-01-11 中兴通讯股份有限公司 印制电路板pcb制作信息的确定方法及装置
KR102503892B1 (ko) 2015-12-31 2023-02-28 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
GB201614147D0 (en) * 2016-08-18 2016-10-05 Trw Ltd Methods of controlling access to keys and of obscuring information and electronic devices
KR102473662B1 (ko) 2017-10-18 2022-12-02 삼성전자주식회사 반도체 소자의 제조 방법
CN110895732A (zh) * 2018-09-12 2020-03-20 欧菲影像技术（广州）有限公司 晶圆映射生产管理方法、装置、系统、介质和计算机设备
KR102110498B1 (ko) * 2018-10-19 2020-05-13 무진전자 주식회사 반도체 공정에서의 지능형 영상 추적 시스템
CN109849105A (zh) * 2018-11-16 2019-06-07 惠科股份有限公司 覆晶薄膜冲切装置、显示装置组装设备及其组装系统
CN109558923A (zh) * 2018-12-04 2019-04-02 北极光电(深圳)有限公司 一种基于二维码的光模块标记系统及方法
US11576263B2 (en) * 2019-01-02 2023-02-07 Novatek Microelectronics Corp. Chip on film package structure and method for reading a code-included pattern on a package structure
JP7401284B2 (ja) * 2019-12-12 2023-12-19 東京エレクトロン株式会社 基板処理装置
CN116541426B (zh) * 2023-06-25 2024-05-14 荣耀终端有限公司 半导体器件的数据存储方法和数据追查方法、电子设备
JP7664503B1 (ja) * 2023-10-30 2025-04-17 リンテック株式会社 半導体装置の製造方法、半導体装置の同一性判定方法、および半導体装置の製造システム
WO2025094558A1 (ja) * 2023-10-30 2025-05-08 リンテック株式会社 半導体装置の製造方法、半導体装置の同一性判定方法、および半導体装置の製造システム

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280039A (ja) 1986-05-30 1987-12-04 Hitachi Ltd マ−キング方法
JPH0393240A (ja) 1989-09-06 1991-04-18 Fujitsu Ltd 樹脂封止型半導体装置の製造方法
JPH118327A (ja) 1997-06-16 1999-01-12 Sony Corp 半導体チップ識別コード付与方法及び半導体チップ管理方法
JPH1126333A (ja) * 1997-06-27 1999-01-29 Oki Electric Ind Co Ltd 半導体装置及びその情報管理システム
US6049624A (en) 1998-02-20 2000-04-11 Micron Technology, Inc. Non-lot based method for assembling integrated circuit devices
US6415977B1 (en) * 2000-08-30 2002-07-09 Micron Technology, Inc. Method and apparatus for marking and identifying a defective die site
JP2002208668A (ja) * 2001-01-10 2002-07-26 Hitachi Ltd 半導体装置およびその製造方法
US7031791B1 (en) * 2001-02-27 2006-04-18 Cypress Semiconductor Corp. Method and system for a reject management protocol within a back-end integrated circuit manufacturing process
JP3757881B2 (ja) 2002-03-08 2006-03-22 株式会社日立製作所 はんだ
JP2004022981A (ja) 2002-06-19 2004-01-22 Renesas Technology Corp 半導体装置およびその製造方法
JP2004193189A (ja) * 2002-12-09 2004-07-08 Matsushita Electric Ind Co Ltd 半導体装置の生産管理システム
US7094633B2 (en) 2003-06-23 2006-08-22 Sandisk Corporation Method for efficiently producing removable peripheral cards
JP2005191367A (ja) 2003-12-26 2005-07-14 Renesas Technology Corp 半導体装置およびその製造方法
JP2005294635A (ja) * 2004-04-01 2005-10-20 Seiko Epson Corp 配線基板および電子部品モジュール
JP2006066701A (ja) 2004-08-27 2006-03-09 Renesas Technology Corp 半導体装置の製造方法
JPWO2006061879A1 (ja) 2004-12-06 2008-06-05 株式会社ルネサステクノロジ 点火装置、半導体装置及びその製造方法
JP4846244B2 (ja) 2005-02-15 2011-12-28 ルネサスエレクトロニクス株式会社 半導体装置
JP4708148B2 (ja) 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US20080011671A1 (en) 2006-07-12 2008-01-17 Yves Syrkos Expandable strainer
JP5291917B2 (ja) 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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US8649896B2 (en) 2014-02-11
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US9287142B2 (en) 2016-03-15
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