JP5281267B2 - 修正可能なゲートスタックメモリ素子 - Google Patents
修正可能なゲートスタックメモリ素子 Download PDFInfo
- Publication number
- JP5281267B2 JP5281267B2 JP2007274887A JP2007274887A JP5281267B2 JP 5281267 B2 JP5281267 B2 JP 5281267B2 JP 2007274887 A JP2007274887 A JP 2007274887A JP 2007274887 A JP2007274887 A JP 2007274887A JP 5281267 B2 JP5281267 B2 JP 5281267B2
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- Prior art keywords
- layer
- gate
- gate stack
- memory cell
- modifiable
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- G11—INFORMATION STORAGE
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- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Description
本発明は、一般的にはメモリに関し、一実施形態では、修正可能な(modifiable)ゲートスタックメモリ素子に関する。
フラッシュメモリなどの不揮発性メモリは、電力が供給されていないときであっても、記憶されたデータを保持する。一般的なタイプの不揮発性メモリは、フラッシュメモリである。フラッシュメモリは、デジタルカメラ、携帯オーディオプレーヤ、無線通信装置、個人用デジタル補助装置(PDA)、および周辺機器などの様々な電子機器において幅広く用いられており、またコンピュータまたはその他の装置内にファームウェアを記憶させるために用いられている。
本発明は、ソース、ドレイン、チャネル、ゲート酸化物層、ゲート電極、および修正可能なゲートスタック層を備えたトランジスタの使用を含む、情報を記憶するためのメモリセル設計および方法を提供する。情報を記憶させるためには、上記修正可能なゲートスタック層内において、電荷蓄積に基づかない物理的変化を生じさせることによって、トランジスタのオン抵抗が変化される。
以下の図面では、異なる図面を通じて、同様の符号は基本的に同一の箇所を示している。これらの図面は、必ずしも互いに相対的な縮尺とはなっていない。その代わりに、本発明の原理を例証する部分は基本的に強調されている。以下の説明では、図面に照らして本発明の様々な実施形態が説明されている。図面は以下の通りである。
50nmノード技術を用いた、DRAMおよびNANDフラッシュメモリなどのメモリ製品の大量生産は、間もなく業界標準となるであろう。メモリ技術におけるノードサイズは50nm以下にまで微細化されたため、既存の技術を用いて微細化するだけでは対応できない様々な技術的問題が生じるであろうことが予想される。代わりに、新しいデバイス構造、新しいプロセス技術、および新しい材料などの新たな手法が求められている。
Claims (10)
- 半導体トランジスタメモリセルであって、
ソース、ドレイン、およびチャネルを有したトランジスタと、
上記チャネル上に配置された厚さ3nm以下のゲート酸化物層と、
ゲート電極と、
上記ゲート酸化物層と上記ゲート電極との間に配置された、修正可能なゲートスタック層とを備えており、
上記修正可能なゲートスタック層は、低導電性材料を含んでおり、当該低導電性材料は、電流が流されたときに高導電性フィラメントを形成することによって、当該ゲートスタック層の導電率を変化させ、
上記修正可能なゲートスタック層の導電率に応じて情報を記憶する、半導体トランジスタメモリセル。 - 上記修正可能なゲートスタック層は固体電解質を含んでいる、請求項1に記載のメモリセル。
- 上記固体電解質はカルコゲナイドガラスを含んでいる、請求項2に記載のメモリセル。
- 上記修正可能なゲートスタック層は、酸化銅、酸化ニッケル、酸化ジルコニウム、酸化チタン、酸化アルミニウム、あるいはSrZrO3膜のうちの少なくとも1つを含んでいる、請求項1に記載のメモリセル。
- 上記修正可能なゲートスタック層はsp3過剰の炭素層を有しており、
上記導電性フィラメントは、上記sp3過剰の炭素層内に形成されたsp2過剰の炭素フィラメントを有している、請求項1に記載のメモリセル。 - メモリセルの製造方法であって、
ソース領域、ドレイン領域、およびチャネル領域によってドープされた基板を備える工程と、
上記チャネル領域上に、厚さ3nm以下のゲート酸化物層を塗布する工程と、
上記ゲート酸化物層上に、低導電性材料の層を修正可能なゲートスタック層として、上記修正可能なゲートスタック層の少なくとも一部が上記ゲート酸化物層に接触するように堆積する工程と、
上記修正可能なゲートスタック層上にゲート電極を、上記ゲート電極の少なくとも一部が上記修正可能なゲートスタック層に接触するように堆積する工程とを含み、
上記低導電性材料は、sp3過剰の炭素層からなり、
上記sp3過剰の炭素層は、上記低導電性材料に電流が流されたときに、該sp3過剰の炭素層内にsp2過剰の炭素フィラメントを有する導電性フィラメントを形成し、
上記導電性フィラメントは、電荷蓄積に基づかない可変の導電率を有する、製造方法。 - 上記修正可能なゲートスタック層を堆積する上記工程は、
カルコゲナイドガラスからなる層を堆積する工程と、
金属からなる層を堆積する工程と、
上記金属の一部を上記カルコゲナイドガラス内に拡散する工程とを含んでいる、請求項6に記載の製造方法。 - 上記修正可能なゲートスタック層を堆積する上記工程は、二成分遷移金属酸化物を堆積する工程を含んでいる、請求項6に記載の製造方法。
- 二成分遷移金属酸化物を堆積する上記工程は、酸化チタン、酸化ニッケル、アルミニウム過剰の酸化物、あるいは酸化ジルコニウムのうちの少なくとも1つを含んだ二成分遷移金属酸化物を堆積する工程を含んでいる、請求項8に記載の製造方法。
- 上記修正可能なゲートスタック層を堆積する上記工程の前に、導電性ゲートプレート層を堆積する工程をさらに含んでいる、請求項6に記載の製造方法。
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-
2006
- 2006-10-27 US US11/588,865 patent/US7915603B2/en not_active Expired - Fee Related
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- 2007-10-23 JP JP2007274887A patent/JP5281267B2/ja not_active Expired - Fee Related
- 2007-10-25 KR KR1020070107981A patent/KR20080038045A/ko not_active Application Discontinuation
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US20080101121A1 (en) | 2008-05-01 |
DE102007011837A1 (de) | 2008-04-30 |
JP2008124452A (ja) | 2008-05-29 |
DE102007011837B4 (de) | 2015-01-29 |
US8097872B2 (en) | 2012-01-17 |
US20080099827A1 (en) | 2008-05-01 |
US7915603B2 (en) | 2011-03-29 |
CN101170132A (zh) | 2008-04-30 |
KR20080038045A (ko) | 2008-05-02 |
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