JP5250787B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5250787B2 JP5250787B2 JP2008330476A JP2008330476A JP5250787B2 JP 5250787 B2 JP5250787 B2 JP 5250787B2 JP 2008330476 A JP2008330476 A JP 2008330476A JP 2008330476 A JP2008330476 A JP 2008330476A JP 5250787 B2 JP5250787 B2 JP 5250787B2
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Description
12A、12B 半導体素子
14 アイランド
16A、16B、16C、16D 接続板
20A、20B、20C、20D、20E、20F、20G、20H リード
22A、22B、22C 半田
23A、23B、23C 半田
24 接続部
26 接続部
28A、28B、28C 半田クリーム
30A、30B、30C 半田クリーム
34 電極
36 電極
38 封止樹脂
50 リードフレーム
52 外枠
54 ユニット
Claims (4)
- アイランドとリードとを含み、第1主面と第2主面とを備えたリードフレームを用意する工程と、
前記アイランドの第1主面に塗布された半田クリームに第1半導体素子を載置し、前記第1半導体素子の電極に塗布された半田クリームに第1接続板の一端を載置し、前記リードの第1主面に塗布された半田クリームに前記第1接続板の他端を載置する工程と、
前記リードフレームの前記第1主面を下向きにした状態で、前記半田クリームを加熱溶融した後に固化し、固化した半田により前記第1半導体素子を前記アイランドの第1主面に固着し、前記半田により前記第1接続板の一端を前記半導体素子の電極に接続し、前記半田により前記第1接続板の他端を前記リードの第1主面に接続する工程と、を備え、
前記接続する工程では、溶融された半田の表面張力により、前記第1半導体素子および前記第1接続板を前記リードフレームに保持した状態とすることを特徴とする半導体装置の製造方法。 - 前記載置する工程では、前記リードフレームの前記第1主面を上向きにした状態で、各前記半田クリームを塗布し、前記第1半導体素子および前記第1接続板を載置し、
前記載置する工程が終了した後に、前記リードフレームの前記第1主面を下方に向けることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記載置する工程の後に、
前記アイランドの第2主面に塗布された半田クリームに第2半導体素子を載置し、前記第2半導体素子の電極に塗布された半田クリームに第2接続板の一端を載置し、前記リードの第2主面に塗布された半田クリームに前記第2接続板の他端を載置する工程を更に備え、
前記接続する工程では、前記半田クリームを加熱溶融することにより、前記第2半導体素子および前記第2接続板の接続も行うことを特徴とする請求項2記載の半導体装置の製造方法。 - 前記接続する工程では、前記第1半導体素子の裏面に形成された金属膜に、溶融された前記半田が付着することを特徴とする請求項3記載の半導体装置の製造方法。
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JP2008330476A JP5250787B2 (ja) | 2008-12-25 | 2008-12-25 | 半導体装置の製造方法 |
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JPH01230292A (ja) * | 1988-03-09 | 1989-09-13 | Fujitsu Ltd | 表面実装部品の半田付け方法 |
JPH0823149A (ja) * | 1994-05-06 | 1996-01-23 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JPH098446A (ja) * | 1995-06-26 | 1997-01-10 | Matsushita Electric Ind Co Ltd | プリント基板の高密度実装方法 |
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