JP5207896B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5207896B2
JP5207896B2 JP2008239751A JP2008239751A JP5207896B2 JP 5207896 B2 JP5207896 B2 JP 5207896B2 JP 2008239751 A JP2008239751 A JP 2008239751A JP 2008239751 A JP2008239751 A JP 2008239751A JP 5207896 B2 JP5207896 B2 JP 5207896B2
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lead frame
semiconductor element
lead
opening
semiconductor device
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JP2010073893A (ja
JP2010073893A5 (enExample
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直 荒井
敏男 小林
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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JP2008239751A 2008-09-18 2008-09-18 半導体装置及びその製造方法 Active JP5207896B2 (ja)

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JP2010073893A5 JP2010073893A5 (enExample) 2011-08-18
JP5207896B2 true JP5207896B2 (ja) 2013-06-12

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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5100715B2 (ja) 2009-07-13 2012-12-19 株式会社東芝 半導体装置及び半導体装置の製造方法
KR101131447B1 (ko) * 2010-10-05 2012-03-29 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
JP5924110B2 (ja) * 2012-05-11 2016-05-25 株式会社ソシオネクスト 半導体装置、半導体装置モジュールおよび半導体装置の製造方法
KR101999114B1 (ko) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 반도체 패키지
US10074628B2 (en) 2013-10-04 2018-09-11 Mediatek Inc. System-in-package and fabrication method thereof
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
KR101819558B1 (ko) * 2015-09-04 2018-01-18 주식회사 네패스 반도체 패키지 및 그 제조방법
KR101809521B1 (ko) * 2015-09-04 2017-12-18 주식회사 네패스 반도체 패키지 및 그 제조방법
EP3151275A3 (en) * 2015-09-11 2017-04-19 MediaTek Inc. System-in-package and fabrication method thereof
KR101944007B1 (ko) * 2015-12-16 2019-01-31 주식회사 네패스 반도체 패키지 및 그 제조방법
JP7096741B2 (ja) 2018-09-11 2022-07-06 株式会社東芝 半導体装置の製造方法
JP2023082375A (ja) * 2021-12-02 2023-06-14 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器
CN119008564A (zh) * 2024-09-04 2024-11-22 甬矽半导体(宁波)有限公司 扇出型封装结构和扇出型封装结构的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294722A (ja) * 1999-04-01 2000-10-20 Nec Corp 積層化チップ半導体装置
JP3649064B2 (ja) * 1999-11-10 2005-05-18 松下電器産業株式会社 半導体装置の製造方法
JP4321758B2 (ja) * 2003-11-26 2009-08-26 カシオ計算機株式会社 半導体装置
JP5378643B2 (ja) * 2006-09-29 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP2008187203A (ja) * 2008-04-25 2008-08-14 Sanyo Electric Co Ltd 半導体装置の製造方法

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