JP5192738B2 - ディジタル・アナログ変換回路 - Google Patents
ディジタル・アナログ変換回路 Download PDFInfo
- Publication number
- JP5192738B2 JP5192738B2 JP2007181972A JP2007181972A JP5192738B2 JP 5192738 B2 JP5192738 B2 JP 5192738B2 JP 2007181972 A JP2007181972 A JP 2007181972A JP 2007181972 A JP2007181972 A JP 2007181972A JP 5192738 B2 JP5192738 B2 JP 5192738B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- current source
- cell
- transistor
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Description
A 14b 150MS/s CMOS DAC with Digital Background Calibration (2006 Symposiumon VLSI Circuits Digest of Technical Papers)
12 電流源セル
14、16 出力端抵抗
18 リファレンス電流源
20、22 トランジスタ
24 電流比較器
26 ロジック回路
28、30 出力配線
32、34 出力端子
36、38 電流源トランジスタ
40、42 電流源用スイッチ
44 ノード
50 電流補正ブロック
52、54 補正用トランジスタ
56、58 補正用スイッチ
60 キャリブレーション用トランジスタ
62 キャリブレーション用スイッチ
Claims (7)
- マトリックス方式で配設した複数の電流源セルを含むディジタル・アナログ変換回路において、該回路は、
前記電流源セルで発生したセル電流を流す経路として、通常動作時のディジタル・アナログ変換用の出力用経路と、キャリブレーション実行用の補正用経路とを含み、
前記電流源セルは、電流源として、所定のバイアス電圧に対して前記セル電流を発生させる第1のトランジスタを含み、
さらに、前記電流源セルは、通常動作時には第1のトランジスタと前記出力用経路とをカスコード接続して前記セル電流を前記出力用経路へと流し、キャリブレーション実行時には第1のトランジスタと前記補正用経路とをカスコード接続して前記セル電流を前記補正用経路へと流し、
該回路は、前記補正用経路で得られる補正値に応じて前記セル電流を補正する補正電流を発生する電流補正手段を含むことを特徴とするディジタル・アナログ変換回路。 - 請求項1に記載のディジタル・アナログ変換回路において、前記出力用経路は、通常動作時に第1のトランジスタとカスコード接続される第2のトランジスタを含み、
前記補正用経路は、キャリブレーション実行時に第1のトランジスタとカスコード接続される第3のトランジスタを含むことを特徴とするディジタル・アナログ変換回路。 - 請求項2に記載のディジタル・アナログ変換回路において、第3のトランジスタは、前記複数の電流源セルごとに配設されることを特徴とするディジタル・アナログ変換回路。
- 請求項2に記載のディジタル・アナログ変換回路において、第3のトランジスタは、前記複数の電流源セルに共通するものが一つだけ配設されることを特徴とするディジタル・アナログ変換回路。
- 請求項1に記載のディジタル・アナログ変換回路において、前記電流補正手段は、前記複数の電流源セルごとに配設されることを特徴とするディジタル・アナログ変換回路。
- 請求項1に記載のディジタル・アナログ変換回路において、前記電流補正手段は、前記複数の電流源セルに共通するものが一つだけ配設されることを特徴とするディジタル・アナログ変換回路。
- 請求項1に記載のディジタル・アナログ変換回路において、前記補正用経路は、前記セル電流と所定のリファレンス電流とを比較する電流比較手段と、該電流比較手段の比較結果に応じて前記補正値を決定するロジック処理手段とを含むことを特徴とするディジタル・アナログ変換回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007181972A JP5192738B2 (ja) | 2007-07-11 | 2007-07-11 | ディジタル・アナログ変換回路 |
US12/142,150 US7683813B2 (en) | 2007-07-11 | 2008-06-19 | Digital-to-analog converter carrying out calibration operation for current source cells |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007181972A JP5192738B2 (ja) | 2007-07-11 | 2007-07-11 | ディジタル・アナログ変換回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009021757A JP2009021757A (ja) | 2009-01-29 |
JP5192738B2 true JP5192738B2 (ja) | 2013-05-08 |
Family
ID=40252660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007181972A Expired - Fee Related JP5192738B2 (ja) | 2007-07-11 | 2007-07-11 | ディジタル・アナログ変換回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7683813B2 (ja) |
JP (1) | JP5192738B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE502006003275D1 (de) * | 2006-09-22 | 2009-05-07 | Siemens Ag | Erhöhung der Verfügbarkeit und Redundanz von Analogstromausgaben |
US7907072B1 (en) * | 2009-09-02 | 2011-03-15 | Freescale Semiconductor, Inc. | Digital-to-analog converter |
US20110068765A1 (en) * | 2009-09-22 | 2011-03-24 | Qualcomm Incorporated | System and method for power calibrating a pulse generator |
US8325072B2 (en) * | 2011-01-10 | 2012-12-04 | Intel Mobile Communications GmbH | Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters |
KR101831696B1 (ko) | 2011-12-06 | 2018-02-23 | 삼성전자주식회사 | 디지털-아날로그 변환 장치 및 동작 방법 |
JP5743924B2 (ja) * | 2012-02-22 | 2015-07-01 | 株式会社東芝 | Daコンバータ |
US9160357B1 (en) * | 2014-04-30 | 2015-10-13 | Qualcomm Incorporated | Residual error sampling and correction circuits in INL DAC calibrations |
KR20160057186A (ko) * | 2014-11-13 | 2016-05-23 | 에스케이하이닉스 주식회사 | 반도체 메모리 시스템 및 그것의 동작 방법 |
US9379883B1 (en) * | 2014-12-16 | 2016-06-28 | Intel Corporation | Digital to analog converter cell for signed operation |
EP3618282B1 (en) | 2018-08-31 | 2021-10-06 | Socionext Inc. | Current generation |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5646619A (en) * | 1995-04-26 | 1997-07-08 | Lucent Technologies Inc. | Self-calibrating high speed D/A converter |
JPH09289450A (ja) | 1996-04-19 | 1997-11-04 | Advantest Corp | Daコンバータ |
US7042374B1 (en) * | 2005-03-21 | 2006-05-09 | National Semiconductor Corporation | Calibration of a current source array |
-
2007
- 2007-07-11 JP JP2007181972A patent/JP5192738B2/ja not_active Expired - Fee Related
-
2008
- 2008-06-19 US US12/142,150 patent/US7683813B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20090015454A1 (en) | 2009-01-15 |
JP2009021757A (ja) | 2009-01-29 |
US7683813B2 (en) | 2010-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5192738B2 (ja) | ディジタル・アナログ変換回路 | |
CN106209108B (zh) | 分段dac | |
JP4901706B2 (ja) | D/a変換器 | |
US8102204B2 (en) | Amplifiers with input offset trim and methods | |
US8179295B2 (en) | Self-calibrated current source and DAC using the same and operation method thereof | |
US20200026993A1 (en) | Neural network circuit | |
US9379728B1 (en) | Self-calibrated digital-to-analog converter | |
JP2004506372A (ja) | 切換型電流源dacのための自己トリミング電流源及び方法 | |
CN106664096B (zh) | 混合数/模转换系统 | |
US9503113B1 (en) | Apparatus for offset trimming and associated methods | |
JP4600167B2 (ja) | 差動増幅回路 | |
WO2010100683A1 (ja) | 基準電流トリミング回路および基準電流トリミング回路を備えたa/d変換器 | |
US8912939B2 (en) | String DAC leakage current cancellation | |
CN110855295A (zh) | 一种数模转换器和控制方法 | |
JP5747761B2 (ja) | デジタル−アナログ変換器及び半導体集積回路 | |
US20180175876A1 (en) | Analog-to-digital converters | |
TWI674763B (zh) | 數位類比轉換器裝置與校正方法 | |
JP4537840B2 (ja) | 電流源セルおよびそれを用いたd/aコンバータ | |
JPH1065542A (ja) | アナログ/ディジタル変換回路 | |
CN111193512B (zh) | 一种数模转换电路 | |
US20130088374A1 (en) | Successive approximation analog to digital converter with comparator input toggling | |
JP4472490B2 (ja) | 半導体集積回路およびそのトリミング方法 | |
JP4596421B2 (ja) | Da変換器 | |
JP2006197052A (ja) | 電流セルマトリクス型da変換器 | |
JP4510987B2 (ja) | Da変換装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081224 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100517 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20110302 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120202 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120214 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120412 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130201 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5192738 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160208 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |