JP5187207B2 - 半導体装置、半導体素子、及び半導体装置の製造方法 - Google Patents
半導体装置、半導体素子、及び半導体装置の製造方法 Download PDFInfo
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- JP5187207B2 JP5187207B2 JP2009015304A JP2009015304A JP5187207B2 JP 5187207 B2 JP5187207 B2 JP 5187207B2 JP 2009015304 A JP2009015304 A JP 2009015304A JP 2009015304 A JP2009015304 A JP 2009015304A JP 5187207 B2 JP5187207 B2 JP 5187207B2
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- electrode
- solder
- solder bump
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
本実施形態の説明に先立ち、本実施形態の基礎となる予備的事項について説明する。
図2〜図6は、本実施形態に係る半導体装置の製造途中の断面図である。
Claims (4)
- 第1の電極が主面に設けられた回路基板と、
前記回路基板の前記主面に形成されたパッドと、
前記第1の電極に対向する第2の電極が主面に設けられた半導体素子と、
前記半導体素子の前記主面において、前記パッドに対向する位置に形成されたスペーサと、
前記第1の電極と前記第2の電極のそれぞれに接合された第1のはんだバンプとを有し、
前記回路基板と前記半導体素子との間に、該回路基板にのみ接合され、該半導体素子には接触するのみで接合されない第2のはんだバンプが形成され、
前記第2の電極は銅ポストであり、
前記スペーサは、前記銅ポストと同じ高さの銅よりなる下側層と、前記第2の電極と比較して、溶融している状態での前記第2のはんだバンプとの反応性が低い材料よりなる上側層とを有し、
前記第2のはんだバンプが前記パッドに接合され、かつ、前記第2のはんだバンプの頂面が前記スペーサの前記上側層に非接合の状態で接触していることを特徴とする半導体装置。 - 前記材料は、有機材料、チタン、クロム、及びステンレスのいずれかよりなることを特徴とする請求項1に記載の半導体装置。
- 主面に形成された電極と、
前記主面に形成されたスペーサとを有し、
前記電極は銅ポストであり、
前記スペーサは、前記銅ポストと同じ高さの銅よりなる下側層と、前記電極と比較して、溶融したはんだに対する反応性が低い材料よりなる上側層とを有することを特徴とする半導体素子。 - 回路基板の主面に設けられた第1の電極と、半導体素子の主面において前記第1の電極に対向する位置に設けられた第2の電極の少なくとも一方に第1のはんだバンプを接合する工程と、
前記回路基板の前記主面に、パッドを介して第2のはんだバンプを接合する工程と、
前記半導体素子の前記主面において、前記パッドに対向する位置にスペーサを形成する工程と、
前記スペーサが前記第2のはんだバンプに当接した状態で、前記第1のはんだバンプと前記第2のはんだバンプを加熱して溶融することにより、前記第2のはんだバンプによって前記回路基板と前記半導体素子との間隔を広げながら、前記第1のはんだバンプを介して前記第1の電極と前記第2の電極を接続する工程と、
を有し、
前記第2の電極は銅ポストであり、
前記スペーサは、前記銅ポストと同じ高さの銅よりなる下側層と、前記第2の電極と比較して、溶融している状態での前記第2のはんだバンプとの反応性が低い材料よりなる上側層とを有することを特徴とする半導体装置の製造方法。
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JP2009015304A JP5187207B2 (ja) | 2009-01-27 | 2009-01-27 | 半導体装置、半導体素子、及び半導体装置の製造方法 |
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JP2010177254A JP2010177254A (ja) | 2010-08-12 |
JP5187207B2 true JP5187207B2 (ja) | 2013-04-24 |
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KR20170017892A (ko) * | 2014-06-20 | 2017-02-15 | 제이에스알 가부시끼가이샤 | 땜납 전극의 제조 방법, 적층체의 제조 방법, 적층체 및 전자 부품 |
US10074624B2 (en) * | 2015-08-07 | 2018-09-11 | Analog Devices, Inc. | Bond pads with differently sized openings |
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JPH06232202A (ja) * | 1993-02-01 | 1994-08-19 | Oki Electric Ind Co Ltd | フリップチップicの実装構造 |
JP4343498B2 (ja) * | 2002-06-27 | 2009-10-14 | 株式会社デンソー | 電子部品の実装構造および実装方法 |
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