JP5173863B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP5173863B2
JP5173863B2 JP2009010156A JP2009010156A JP5173863B2 JP 5173863 B2 JP5173863 B2 JP 5173863B2 JP 2009010156 A JP2009010156 A JP 2009010156A JP 2009010156 A JP2009010156 A JP 2009010156A JP 5173863 B2 JP5173863 B2 JP 5173863B2
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JP
Japan
Prior art keywords
insulating film
interlayer insulating
wiring
semiconductor device
film
Prior art date
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Active
Application number
JP2009010156A
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English (en)
Japanese (ja)
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JP2010171072A (ja
JP2010171072A5 (https=
Inventor
誠 筒江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2009010156A priority Critical patent/JP5173863B2/ja
Priority to PCT/JP2009/005151 priority patent/WO2010084535A1/ja
Publication of JP2010171072A publication Critical patent/JP2010171072A/ja
Priority to US13/038,974 priority patent/US8564136B2/en
Publication of JP2010171072A5 publication Critical patent/JP2010171072A5/ja
Application granted granted Critical
Publication of JP5173863B2 publication Critical patent/JP5173863B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6538—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665—Porous materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
JP2009010156A 2009-01-20 2009-01-20 半導体装置およびその製造方法 Active JP5173863B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009010156A JP5173863B2 (ja) 2009-01-20 2009-01-20 半導体装置およびその製造方法
PCT/JP2009/005151 WO2010084535A1 (ja) 2009-01-20 2009-10-05 半導体装置およびその製造方法
US13/038,974 US8564136B2 (en) 2009-01-20 2011-03-02 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009010156A JP5173863B2 (ja) 2009-01-20 2009-01-20 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2010171072A JP2010171072A (ja) 2010-08-05
JP2010171072A5 JP2010171072A5 (https=) 2011-03-24
JP5173863B2 true JP5173863B2 (ja) 2013-04-03

Family

ID=42355614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009010156A Active JP5173863B2 (ja) 2009-01-20 2009-01-20 半導体装置およびその製造方法

Country Status (3)

Country Link
US (1) US8564136B2 (https=)
JP (1) JP5173863B2 (https=)
WO (1) WO2010084535A1 (https=)

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GB201110117D0 (en) * 2011-06-16 2011-07-27 Fujifilm Mfg Europe Bv method and device for manufacturing a barrie layer on a flexible substrate
JP5925611B2 (ja) 2012-06-21 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101998788B1 (ko) 2013-04-22 2019-07-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9117822B1 (en) * 2014-04-29 2015-08-25 Globalfoundries Inc. Methods and structures for back end of line integration
WO2017105447A1 (en) * 2015-12-16 2017-06-22 Intel Corporation Methods and apparatuses to provide ordered porosity
US9842804B2 (en) * 2016-01-04 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for reducing dual damascene distortion
US20180151716A1 (en) 2016-11-28 2018-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
CN110537251B (zh) 2017-04-25 2023-07-04 三菱电机株式会社 半导体装置
US10629478B2 (en) 2017-08-22 2020-04-21 International Business Machines Corporation Dual-damascene formation with dielectric spacer and thin liner
WO2020000376A1 (zh) 2018-06-29 2020-01-02 长江存储科技有限责任公司 半导体结构及其形成方法
WO2021144940A1 (ja) 2020-01-16 2021-07-22 昭和電工マテリアルズ株式会社 研磨剤、研磨剤用貯蔵液及び研磨方法

Family Cites Families (21)

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TW502381B (en) * 2001-04-24 2002-09-11 United Microelectronics Corp Manufacturing method of damascene structure
JP3657576B2 (ja) * 2001-06-12 2005-06-08 株式会社東芝 半導体装置の製造方法
TW550642B (en) 2001-06-12 2003-09-01 Toshiba Corp Semiconductor device with multi-layer interconnect and method fabricating the same
US20030213617A1 (en) * 2002-05-20 2003-11-20 Subramanian Karthikeyan Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device
US6686662B2 (en) * 2002-05-21 2004-02-03 Agere Systems Inc. Semiconductor device barrier layer
US7186640B2 (en) * 2002-06-20 2007-03-06 Chartered Semiconductor Manufacturing Ltd. Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics
US6893985B2 (en) * 2003-03-31 2005-05-17 Intel Corporation UV-activated dielectric layer
US7052990B2 (en) * 2003-09-03 2006-05-30 Infineon Technologies Ag Sealed pores in low-k material damascene conductive structures
US7405147B2 (en) * 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
JP2005223195A (ja) 2004-02-06 2005-08-18 Renesas Technology Corp 層間絶縁膜の形成方法および半導体装置の製造方法
JP2006024811A (ja) * 2004-07-09 2006-01-26 Sony Corp 半導体装置の製造方法
US7732349B2 (en) 2004-11-30 2010-06-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of insulating film and semiconductor device
JP4749133B2 (ja) * 2004-11-30 2011-08-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7135402B2 (en) * 2005-02-01 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing pores of low-k dielectrics using CxHy
US7338893B2 (en) * 2005-11-23 2008-03-04 Texas Instruments Incorporated Integration of pore sealing liner into dual-damascene methods and devices
US7564136B2 (en) * 2006-02-24 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration scheme for Cu/low-k interconnects
WO2007099428A1 (en) * 2006-02-28 2007-09-07 Stmicroelectronics (Crolles 2) Sas Metal interconnects in a dielectric material
JP4788415B2 (ja) 2006-03-15 2011-10-05 ソニー株式会社 半導体装置の製造方法
US7435674B2 (en) * 2006-03-27 2008-10-14 International Business Machines Corporation Dielectric interconnect structures and methods for forming the same
US7329956B1 (en) * 2006-09-12 2008-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene cleaning method
US7947565B2 (en) * 2007-02-07 2011-05-24 United Microelectronics Corp. Forming method of porous low-k layer and interconnect process

Also Published As

Publication number Publication date
US20110147882A1 (en) 2011-06-23
JP2010171072A (ja) 2010-08-05
US8564136B2 (en) 2013-10-22
WO2010084535A1 (ja) 2010-07-29

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