JP5167022B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5167022B2
JP5167022B2 JP2008204141A JP2008204141A JP5167022B2 JP 5167022 B2 JP5167022 B2 JP 5167022B2 JP 2008204141 A JP2008204141 A JP 2008204141A JP 2008204141 A JP2008204141 A JP 2008204141A JP 5167022 B2 JP5167022 B2 JP 5167022B2
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JP
Japan
Prior art keywords
sealing body
metal substrate
substrate
metal
molding die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008204141A
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English (en)
Japanese (ja)
Other versions
JP2010040911A5 (https=
JP2010040911A (ja
Inventor
孝治 古川
嗣雄 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008204141A priority Critical patent/JP5167022B2/ja
Publication of JP2010040911A publication Critical patent/JP2010040911A/ja
Publication of JP2010040911A5 publication Critical patent/JP2010040911A5/ja
Application granted granted Critical
Publication of JP5167022B2 publication Critical patent/JP5167022B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2008204141A 2008-08-07 2008-08-07 半導体装置の製造方法 Expired - Fee Related JP5167022B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008204141A JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008204141A JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010040911A JP2010040911A (ja) 2010-02-18
JP2010040911A5 JP2010040911A5 (https=) 2011-09-15
JP5167022B2 true JP5167022B2 (ja) 2013-03-21

Family

ID=42013110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008204141A Expired - Fee Related JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP5167022B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6466252B2 (ja) 2014-06-19 2019-02-06 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
JP6457206B2 (ja) 2014-06-19 2019-01-23 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
CN105280567B (zh) 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
JP6304435B1 (ja) * 2017-07-25 2018-04-04 第一精工株式会社 基材の変形止め機構及び基材の変形止め方法
CN117939794B (zh) * 2024-03-20 2024-05-28 大连保税区金宝至电子有限公司 一种分布式外引脚覆铜陶瓷基板的加工方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62124747A (ja) * 1985-11-25 1987-06-06 Sharp Corp 自動モ−ルド装置に於けるカルブレイク方法
JP2000299329A (ja) * 1999-04-12 2000-10-24 Mitsubishi Electric Corp 樹脂パッケージ型半導体装置の製造装置及び製造方法
JP4106844B2 (ja) * 2000-02-22 2008-06-25 沖電気工業株式会社 樹脂封止半導体装置のリード部のゲートブレーク方法
JP2002016181A (ja) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd 半導体装置、その製造方法、及び電着フレーム
JP2004214265A (ja) * 2002-12-27 2004-07-29 Kyushu Hitachi Maxell Ltd 半導体装置および半導体装置の製造方法
JP2006269486A (ja) * 2005-03-22 2006-10-05 Renesas Technology Corp 半導体装置の製造方法
JP2006351835A (ja) * 2005-06-16 2006-12-28 Aoi Electronics Co Ltd 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
JP2010040911A (ja) 2010-02-18

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