JP5166903B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5166903B2
JP5166903B2 JP2008029141A JP2008029141A JP5166903B2 JP 5166903 B2 JP5166903 B2 JP 5166903B2 JP 2008029141 A JP2008029141 A JP 2008029141A JP 2008029141 A JP2008029141 A JP 2008029141A JP 5166903 B2 JP5166903 B2 JP 5166903B2
Authority
JP
Japan
Prior art keywords
pads
chip
semiconductor chip
memory
plan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008029141A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009188328A (ja
JP2009188328A5 (enExample
Inventor
稔 篠原
道昭 杉山
尊臣 西
正昭 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008029141A priority Critical patent/JP5166903B2/ja
Publication of JP2009188328A publication Critical patent/JP2009188328A/ja
Publication of JP2009188328A5 publication Critical patent/JP2009188328A5/ja
Application granted granted Critical
Publication of JP5166903B2 publication Critical patent/JP5166903B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Semiconductor Memories (AREA)
  • Credit Cards Or The Like (AREA)
JP2008029141A 2008-02-08 2008-02-08 半導体装置 Expired - Fee Related JP5166903B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008029141A JP5166903B2 (ja) 2008-02-08 2008-02-08 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008029141A JP5166903B2 (ja) 2008-02-08 2008-02-08 半導体装置

Publications (3)

Publication Number Publication Date
JP2009188328A JP2009188328A (ja) 2009-08-20
JP2009188328A5 JP2009188328A5 (enExample) 2011-03-24
JP5166903B2 true JP5166903B2 (ja) 2013-03-21

Family

ID=41071248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008029141A Expired - Fee Related JP5166903B2 (ja) 2008-02-08 2008-02-08 半導体装置

Country Status (1)

Country Link
JP (1) JP5166903B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG185491A1 (en) * 2010-05-20 2012-12-28 Ev Group E Thallner Gmbh Method for producing chip stacks as well as a carrier for executing the method
US9121900B2 (en) * 2011-12-02 2015-09-01 Sandisk Technologies Inc. Systems and methods for sensing signals communicated with a host device or on an interface of plug-in card when there is lack of access to sensing points
JP6122290B2 (ja) 2011-12-22 2017-04-26 三星電子株式会社Samsung Electronics Co.,Ltd. 再配線層を有する半導体パッケージ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217354A (ja) * 2001-01-15 2002-08-02 Shinko Electric Ind Co Ltd 半導体装置
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
JP2007096071A (ja) * 2005-09-29 2007-04-12 Toshiba Corp 半導体メモリカード
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
JP4900661B2 (ja) * 2006-02-22 2012-03-21 ルネサスエレクトロニクス株式会社 不揮発性記憶装置

Also Published As

Publication number Publication date
JP2009188328A (ja) 2009-08-20

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