JP5164833B2 - 印刷可能な半導体構造の製造方法 - Google Patents

印刷可能な半導体構造の製造方法 Download PDF

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JP5164833B2
JP5164833B2 JP2008514820A JP2008514820A JP5164833B2 JP 5164833 B2 JP5164833 B2 JP 5164833B2 JP 2008514820 A JP2008514820 A JP 2008514820A JP 2008514820 A JP2008514820 A JP 2008514820A JP 5164833 B2 JP5164833 B2 JP 5164833B2
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printable semiconductor
semiconductor element
silicon wafer
wafer
etching
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JP2009508322A5 (https=
JP2009508322A (ja
Inventor
ラルフ ジー． ヌゾー，
ジョン エー． ロジャース，
エティエンヌ メナード，
ケオン ジャエ リー，
ダール−ヤン カン，
ユーガン サン，
マシュー メイトル，
ツェンタオ ツ，
フエン チョー コー，
シャウン マック，
Original Assignee
ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ
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Priority claimed from US11/145,542 external-priority patent/US7557367B2/en
Application filed by ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ filed Critical ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ
Priority claimed from PCT/US2006/021161 external-priority patent/WO2006130721A2/en
Publication of JP2009508322A publication Critical patent/JP2009508322A/ja
Publication of JP2009508322A5 publication Critical patent/JP2009508322A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
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    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
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    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
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    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3822—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
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    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2008514820A 2005-06-02 2006-06-01 印刷可能な半導体構造の製造方法 Active JP5164833B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US11/145,542 US7557367B2 (en) 2004-06-04 2005-06-02 Stretchable semiconductor elements and stretchable electrical circuits
PCT/US2005/019354 WO2005122285A2 (en) 2004-06-04 2005-06-02 Methods and devices for fabricating and assembling printable semiconductor elements
USPCT/US2005/019354 2005-06-02
US11/145,542 2005-06-02
US11/145,574 US7622367B1 (en) 2004-06-04 2005-06-02 Methods and devices for fabricating and assembling printable semiconductor elements
US11/145,574 2005-06-02
PCT/US2006/021161 WO2006130721A2 (en) 2005-06-02 2006-06-01 Printable semiconductor structures and related methods of making and assembling

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012246602A Division JP5734261B2 (ja) 2005-06-02 2012-11-08 印刷可能な半導体構造、並びに関連する製造方法及び組立方法

Publications (3)

Publication Number Publication Date
JP2009508322A JP2009508322A (ja) 2009-02-26
JP2009508322A5 JP2009508322A5 (https=) 2012-05-10
JP5164833B2 true JP5164833B2 (ja) 2013-03-21

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JP2008514820A Active JP5164833B2 (ja) 2005-06-02 2006-06-01 印刷可能な半導体構造の製造方法
JP2006154975A Active JP5297581B2 (ja) 2005-06-02 2006-06-02 エラストマースタンプへの接着の動的コントロールによるパターン転送印刷
JP2012246602A Active JP5734261B2 (ja) 2005-06-02 2012-11-08 印刷可能な半導体構造、並びに関連する製造方法及び組立方法
JP2013095896A Active JP5701331B2 (ja) 2005-06-02 2013-04-30 エラストマースタンプへの接着の動的コントロールによるパターン転送印刷
JP2014177486A Active JP6002725B2 (ja) 2005-06-02 2014-09-01 印刷可能な半導体構造、並びに関連する製造方法及び組立方法

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JP2006154975A Active JP5297581B2 (ja) 2005-06-02 2006-06-02 エラストマースタンプへの接着の動的コントロールによるパターン転送印刷
JP2012246602A Active JP5734261B2 (ja) 2005-06-02 2012-11-08 印刷可能な半導体構造、並びに関連する製造方法及び組立方法
JP2013095896A Active JP5701331B2 (ja) 2005-06-02 2013-04-30 エラストマースタンプへの接着の動的コントロールによるパターン転送印刷
JP2014177486A Active JP6002725B2 (ja) 2005-06-02 2014-09-01 印刷可能な半導体構造、並びに関連する製造方法及び組立方法

Country Status (3)

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EP (2) EP2937896B1 (https=)
JP (5) JP5164833B2 (https=)
KR (2) KR101308548B1 (https=)

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KR101221871B1 (ko) 2009-12-07 2013-01-15 한국전자통신연구원 반도체 소자의 제조방법
US9442285B2 (en) * 2011-01-14 2016-09-13 The Board Of Trustees Of The University Of Illinois Optical component array having adjustable curvature
KR102211596B1 (ko) 2012-12-28 2021-02-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6124051B2 (ja) * 2013-02-01 2017-05-10 国立大学法人九州工業大学 細胞培養シート、およびその製造方法、並びにこれを用いた細胞培養容器
JP6078920B2 (ja) 2013-02-13 2017-02-15 国立大学法人広島大学 薄膜形成方法、及びそれを用いて作製した半導体基板ならびに電子デバイス
US10002700B2 (en) 2013-02-27 2018-06-19 Qualcomm Incorporated Vertical-coupling transformer with an air-gap structure
US9634645B2 (en) 2013-03-14 2017-04-25 Qualcomm Incorporated Integration of a replica circuit and a transformer above a dielectric substrate
US9449753B2 (en) 2013-08-30 2016-09-20 Qualcomm Incorporated Varying thickness inductor
WO2015156874A2 (en) * 2014-01-15 2015-10-15 The Regents Of The Univerity Of Michigan Integration of epitaxial lift-off solar cells with mini-parabolic concentrator arrays via printing method
US9906318B2 (en) 2014-04-18 2018-02-27 Qualcomm Incorporated Frequency multiplexer
CN117198903A (zh) * 2014-07-20 2023-12-08 艾克斯展示公司技术有限公司 用于微转贴印刷的设备及方法
DE112015004894B4 (de) * 2014-10-28 2022-11-03 Analog Devices, Inc. Transferdruckverfahren
US10748793B1 (en) 2019-02-13 2020-08-18 X Display Company Technology Limited Printing component arrays with different orientations
TWI728364B (zh) * 2019-05-21 2021-05-21 國立陽明交通大學 氮化鎵異質整合於矽基板之半導體結構及其製造方法
US11062936B1 (en) 2019-12-19 2021-07-13 X Display Company Technology Limited Transfer stamps with multiple separate pedestals
KR102300920B1 (ko) * 2020-11-09 2021-09-13 한국과학기술원 InP 기판을 이용한 소자 제조 방법
JPWO2024209537A1 (https=) * 2023-04-04 2024-10-10
CN120050969B (zh) * 2025-02-25 2025-11-14 上海新微半导体有限公司 锑化物hemt结构、外延结构及其制备方法

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