JP5150022B2 - メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法 - Google Patents

メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法 Download PDF

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Publication number
JP5150022B2
JP5150022B2 JP2000608421A JP2000608421A JP5150022B2 JP 5150022 B2 JP5150022 B2 JP 5150022B2 JP 2000608421 A JP2000608421 A JP 2000608421A JP 2000608421 A JP2000608421 A JP 2000608421A JP 5150022 B2 JP5150022 B2 JP 5150022B2
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Japan
Prior art keywords
memory cell
layer
cell capacitor
platinum
capacitor plate
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Expired - Fee Related
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JP2000608421A
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English (en)
Japanese (ja)
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JP2002540626A5 (https=
JP2002540626A (ja
Inventor
ケイル・ダグラス・エル．
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

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  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2000608421A 1999-03-31 2000-03-30 メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法 Expired - Fee Related JP5150022B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/281,866 US6268260B1 (en) 1999-03-31 1999-03-31 Methods of forming memory cell capacitor plates in memory cell capacitor structures
US09/281,866 1999-03-31
PCT/US2000/008638 WO2000059011A2 (en) 1999-03-31 2000-03-30 Memory cell capacitor plate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012118381A Division JP2012186499A (ja) 1999-03-31 2012-05-24 メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法

Publications (3)

Publication Number Publication Date
JP2002540626A JP2002540626A (ja) 2002-11-26
JP2002540626A5 JP2002540626A5 (https=) 2007-05-31
JP5150022B2 true JP5150022B2 (ja) 2013-02-20

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Family Applications (2)

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JP2000608421A Expired - Fee Related JP5150022B2 (ja) 1999-03-31 2000-03-30 メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法
JP2012118381A Withdrawn JP2012186499A (ja) 1999-03-31 2012-05-24 メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法

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JP2012118381A Withdrawn JP2012186499A (ja) 1999-03-31 2012-05-24 メモリセルキャパシタ構造におけるメモリセルキャパシタプレートの形成方法

Country Status (4)

Country Link
US (1) US6268260B1 (https=)
JP (2) JP5150022B2 (https=)
KR (2) KR100751744B1 (https=)
WO (1) WO2000059011A2 (https=)

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* Cited by examiner, † Cited by third party
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DE10022656B4 (de) 2000-04-28 2006-07-06 Infineon Technologies Ag Verfahren zum Entfernen von Strukturen
KR100359299B1 (en) * 2001-03-26 2002-11-07 Samsung Electronics Co Ltd Semiconductor memory device having resist pattern and method for forming metal contact thereof
KR100487558B1 (ko) * 2003-03-03 2005-05-03 삼성전자주식회사 반실린더형 캐패시터를 갖는 강유전체 메모리 소자 및 그제조방법
KR100615092B1 (ko) * 2004-08-16 2006-08-23 삼성전자주식회사 노드 도전막 패턴들에 각각 자기 정렬시킨 하부 전극들을갖는 에프. 램들 및 그 형성방법들
KR20130114280A (ko) * 2007-06-12 2013-10-16 후지필름 가부시키가이샤 네가티브 톤 현상용 레지스트 조성물 및 이것을 사용한 패턴형성방법
KR101435520B1 (ko) 2008-08-11 2014-09-01 삼성전자주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
KR101540083B1 (ko) * 2008-10-22 2015-07-30 삼성전자주식회사 반도체 소자의 패턴 형성 방법

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JP2799566B2 (ja) * 1985-11-14 1998-09-17 セイコーインスツルメンツ株式会社 半導体装置の製造方法
US5283201A (en) 1988-05-17 1994-02-01 Advanced Power Technology, Inc. High density power device fabrication process
WO1991016731A1 (fr) 1990-04-24 1991-10-31 Seiko Epson Corporation Dispositif a semiconducteur avec materiau ferro-electrique et procede de production de ce dispositif
US5142437A (en) 1991-06-13 1992-08-25 Ramtron Corporation Conducting electrode layers for ferroelectric capacitors in integrated circuits and method
JPH06151749A (ja) * 1992-11-04 1994-05-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5392189A (en) 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
JP2550852B2 (ja) * 1993-04-12 1996-11-06 日本電気株式会社 薄膜キャパシタの製造方法
JP3267389B2 (ja) * 1993-06-23 2002-03-18 沖電気工業株式会社 メモリセルのキャパシタ形成方法
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
JPH0897219A (ja) * 1994-09-26 1996-04-12 Hitachi Ltd 導電体の形成方法
US5464786A (en) 1994-10-24 1995-11-07 Micron Technology, Inc. Method for forming a capacitor having recessed lateral reaction barrier layer edges
US5801916A (en) 1995-11-13 1998-09-01 Micron Technology, Inc. Pre-patterned contact fill capacitor for dielectric etch protection
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JPH10107223A (ja) * 1996-10-02 1998-04-24 Texas Instr Japan Ltd 誘電体キャパシタ及び誘電体メモリ装置と、これらの製造方法
JP3114640B2 (ja) * 1997-02-14 2000-12-04 日本電気株式会社 半導体装置の製造方法
JPH10289985A (ja) * 1997-04-14 1998-10-27 Mitsubishi Electric Corp キャパシタを有する半導体装置の製造方法
KR100230418B1 (ko) * 1997-04-17 1999-11-15 윤종용 백금족 금속층 형성방법 및 이를 이용한 커패시터 제조방법
JPH10335604A (ja) * 1997-06-02 1998-12-18 Mitsubishi Electric Corp 半導体メモリ装置及びその製造方法
JPH10340871A (ja) * 1997-06-06 1998-12-22 Toshiba Corp 研磨方法及び半導体装置の製造方法
JP3569112B2 (ja) * 1997-07-17 2004-09-22 株式会社東芝 半導体集積回路およびその製造方法
JPH1187644A (ja) * 1997-09-01 1999-03-30 Sony Corp Ｄｒａｍの製造方法
JPH11214653A (ja) * 1998-01-28 1999-08-06 Toshiba Corp 半導体装置およびその製造方法
JP3226166B2 (ja) * 1998-02-06 2001-11-05 ソニー株式会社 強誘電体キャパシタおよびその製造方法並びに強誘電体メモリ
JP3905977B2 (ja) * 1998-05-22 2007-04-18 株式会社東芝 半導体装置の製造方法
JP4809961B2 (ja) * 1998-08-07 2011-11-09 株式会社東芝 半導体装置及びその製造方法
JP2000243931A (ja) * 1998-12-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
JP2000260957A (ja) * 1999-03-12 2000-09-22 Hitachi Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
WO2000059011A2 (en) 2000-10-05
KR20060129099A (ko) 2006-12-14
US6268260B1 (en) 2001-07-31
JP2012186499A (ja) 2012-09-27
KR100751744B1 (ko) 2007-08-24
WO2000059011A3 (en) 2001-02-22
KR20020003227A (ko) 2002-01-10
JP2002540626A (ja) 2002-11-26
KR100751745B1 (ko) 2007-08-27

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