JP5144964B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5144964B2 JP5144964B2 JP2007149793A JP2007149793A JP5144964B2 JP 5144964 B2 JP5144964 B2 JP 5144964B2 JP 2007149793 A JP2007149793 A JP 2007149793A JP 2007149793 A JP2007149793 A JP 2007149793A JP 5144964 B2 JP5144964 B2 JP 5144964B2
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- oxygen
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- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims description 133
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 239000001301 oxygen Substances 0.000 claims description 156
- 229910052760 oxygen Inorganic materials 0.000 claims description 156
- 239000000758 substrate Substances 0.000 claims description 132
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 128
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 73
- -1 oxygen ions Chemical class 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 25
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 22
- 238000002513 implantation Methods 0.000 claims description 22
- 238000001039 wet etching Methods 0.000 claims description 15
- 241000293849 Cordylanthus Species 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000001590 oxidative effect Effects 0.000 claims description 11
- 239000011261 inert gas Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000005530 etching Methods 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 238000001312 dry etching Methods 0.000 description 12
- 238000012986 modification Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 6
- 229910001882 dioxygen Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
12 酸化膜
14 窒化膜
16 凹部
18 酸化領域
20 開口部
22 フォトレジスト
24 第1酸素含有領域
26 第1酸化領域
28 凸部
30 ポリシリコン膜
32 第2酸素含有領域
34 第2酸化領域
38 絶縁膜
40 ゲート
42 ソース
44 ドレイン
Claims (6)
- 半導体基板の一部に酸素イオン注入を行うことで第1酸素含有領域を形成する工程と、
前記半導体基板に熱処理を行い、前記第1酸素含有領域に含まれる酸素を用いて前記第1酸素含有領域を酸化させることで、前記第1酸素含有領域を第1酸化領域とする工程と、
前記第1酸化領域を除去することで前記半導体基板に凹部を形成する工程と、を有し、
前記半導体基板はシリコン基板であり、
前記第1酸素含有領域を形成する工程は、前記半導体基板上に形成されたポリシリコン膜をマスクとして前記半導体基板の一部に前記酸素イオン注入を行うと同時に、前記ポリシリコン膜に前記酸素イオン注入を行うことで前記ポリシリコン膜に第2酸素含有領域を形成する工程を含み、
前記第1酸化領域とする工程は、前記半導体基板に熱処理を行い、前記第1酸素含有領域に含まれる酸素を用いて前記第1酸素含有領域を酸化させると同時に、前記第2酸素含有領域に含まれる酸素を用いて前記第2酸素含有領域を酸化させることで、前記第2酸素含有領域を第2酸化領域とする工程を含み、
前記凹部を形成する工程は、前記第1酸化領域を除去すると同時に、前記第2酸化領域を除去する工程を含むことを特徴とする半導体装置の製造方法。 - 前記第1酸素含有領域を形成する工程は、複数の異なる注入エネルギーで前記酸素イオン注入を行うことで前記第1酸素含有領域を形成する工程であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記凹部を形成する工程は、ウエットエッチングにより前記第1酸化領域を除去することで前記凹部を形成する工程であることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記凹部を形成する工程の後、前記半導体基板を熱酸化することで前記凹部の表面に酸化膜を形成する工程と、
前記酸化膜をウエットエッチングで除去する工程と、を有することを特徴とする請求項1から3のいずれか一項記載の半導体装置の製造方法。 - 前記熱処理はバーズビークが生じないように行われることを特徴とする請求項1から4のいずれか一項記載の半導体装置の製造方法。
- 前記熱処理は不活性ガス雰囲気中で行われることを特徴とする請求項5記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007149793A JP5144964B2 (ja) | 2007-06-05 | 2007-06-05 | 半導体装置の製造方法 |
US12/134,087 US7871896B2 (en) | 2007-06-05 | 2008-06-05 | Precision trench formation through oxide region formation for a semiconductor device |
US12/961,352 US8354326B2 (en) | 2007-06-05 | 2010-12-06 | Precision trench formation through oxide region formation for a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007149793A JP5144964B2 (ja) | 2007-06-05 | 2007-06-05 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012257365A Division JP5508505B2 (ja) | 2012-11-26 | 2012-11-26 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008305870A JP2008305870A (ja) | 2008-12-18 |
JP5144964B2 true JP5144964B2 (ja) | 2013-02-13 |
Family
ID=40096263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007149793A Expired - Fee Related JP5144964B2 (ja) | 2007-06-05 | 2007-06-05 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7871896B2 (ja) |
JP (1) | JP5144964B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5423613B2 (ja) * | 2010-08-17 | 2014-02-19 | 三菱電機株式会社 | 半導体装置の製造方法 |
US8823126B2 (en) * | 2012-05-04 | 2014-09-02 | Hong Kong Applied Science and Technology Research Institute Company Limited | Low cost backside illuminated CMOS image sensor package with high integration |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5931067A (ja) * | 1982-08-14 | 1984-02-18 | Matsushita Electric Works Ltd | 縦型トランジスタの製法 |
JPS6084831A (ja) * | 1983-10-15 | 1985-05-14 | Matsushita Electronics Corp | 半導体装置の製造方法 |
JPH01105543A (ja) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH025525A (ja) * | 1988-06-24 | 1990-01-10 | Nec Corp | 半導体基板のエッチング方法 |
JPH0562926A (ja) * | 1991-09-03 | 1993-03-12 | Sharp Corp | 半導体装置の製造方法 |
JPH06275576A (ja) * | 1993-03-22 | 1994-09-30 | Nec Kansai Ltd | 半導体装置の製造方法 |
US5895252A (en) * | 1994-05-06 | 1999-04-20 | United Microelectronics Corporation | Field oxidation by implanted oxygen (FIMOX) |
KR0176153B1 (ko) * | 1995-05-30 | 1999-04-15 | 김광호 | 반도체 장치의 소자분리막 및 그 형성방법 |
KR100343471B1 (ko) * | 2000-08-16 | 2002-07-18 | 박종섭 | 반도체 소자 제조방법 |
US6531410B2 (en) * | 2001-02-27 | 2003-03-11 | International Business Machines Corporation | Intrinsic dual gate oxide MOSFET using a damascene gate process |
KR100450667B1 (ko) * | 2001-10-09 | 2004-10-01 | 삼성전자주식회사 | 유효 채널 길이를 연장시킬 수 있는 반도체 소자의 홈 형성방법 |
US7176104B1 (en) * | 2004-06-08 | 2007-02-13 | Integrated Device Technology, Inc. | Method for forming shallow trench isolation structure with deep oxide region |
-
2007
- 2007-06-05 JP JP2007149793A patent/JP5144964B2/ja not_active Expired - Fee Related
-
2008
- 2008-06-05 US US12/134,087 patent/US7871896B2/en active Active
-
2010
- 2010-12-06 US US12/961,352 patent/US8354326B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20110081767A1 (en) | 2011-04-07 |
US20080305614A1 (en) | 2008-12-11 |
JP2008305870A (ja) | 2008-12-18 |
US7871896B2 (en) | 2011-01-18 |
US8354326B2 (en) | 2013-01-15 |
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