JP5144170B2 - 半導体装置の実装方法 - Google Patents

半導体装置の実装方法 Download PDF

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Publication number
JP5144170B2
JP5144170B2 JP2007213554A JP2007213554A JP5144170B2 JP 5144170 B2 JP5144170 B2 JP 5144170B2 JP 2007213554 A JP2007213554 A JP 2007213554A JP 2007213554 A JP2007213554 A JP 2007213554A JP 5144170 B2 JP5144170 B2 JP 5144170B2
Authority
JP
Japan
Prior art keywords
semiconductor device
terminal
connection
circuit
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007213554A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009049170A5 (enrdf_load_stackoverflow
JP2009049170A (ja
Inventor
俊彦 秋葉
斉尚 佐藤
孝洋 内藤
一繁 山岸
文次 安村
尚宏 槇平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007213554A priority Critical patent/JP5144170B2/ja
Publication of JP2009049170A publication Critical patent/JP2009049170A/ja
Publication of JP2009049170A5 publication Critical patent/JP2009049170A5/ja
Application granted granted Critical
Publication of JP5144170B2 publication Critical patent/JP5144170B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007213554A 2007-08-20 2007-08-20 半導体装置の実装方法 Expired - Fee Related JP5144170B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007213554A JP5144170B2 (ja) 2007-08-20 2007-08-20 半導体装置の実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007213554A JP5144170B2 (ja) 2007-08-20 2007-08-20 半導体装置の実装方法

Publications (3)

Publication Number Publication Date
JP2009049170A JP2009049170A (ja) 2009-03-05
JP2009049170A5 JP2009049170A5 (enrdf_load_stackoverflow) 2010-09-30
JP5144170B2 true JP5144170B2 (ja) 2013-02-13

Family

ID=40501128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007213554A Expired - Fee Related JP5144170B2 (ja) 2007-08-20 2007-08-20 半導体装置の実装方法

Country Status (1)

Country Link
JP (1) JP5144170B2 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5342422B2 (ja) 2009-12-10 2013-11-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN110473839B (zh) 2018-05-11 2025-03-21 三星电子株式会社 半导体封装系统
US10991638B2 (en) 2018-05-14 2021-04-27 Samsung Electronics Co., Ltd. Semiconductor package system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271966A (ja) * 1987-04-28 1988-11-09 Nec Corp 半導体集積回路
JPH03172782A (ja) * 1989-12-01 1991-07-26 Hitachi Ltd 半導体集積回路
JP4509437B2 (ja) * 2000-09-11 2010-07-21 Ｈｏｙａ株式会社 多層配線基板の製造方法
JP2004335858A (ja) * 2003-05-09 2004-11-25 Murata Mfg Co Ltd 電子部品およびそれを用いた電子機器
JP2004078996A (ja) * 2003-11-17 2004-03-11 Renesas Technology Corp データ処理装置
JP2007115904A (ja) * 2005-10-20 2007-05-10 Renesas Technology Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2009049170A (ja) 2009-03-05

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