JP4539396B2 - 半導体装置の実装構造 - Google Patents
半導体装置の実装構造 Download PDFInfo
- Publication number
- JP4539396B2 JP4539396B2 JP2005090578A JP2005090578A JP4539396B2 JP 4539396 B2 JP4539396 B2 JP 4539396B2 JP 2005090578 A JP2005090578 A JP 2005090578A JP 2005090578 A JP2005090578 A JP 2005090578A JP 4539396 B2 JP4539396 B2 JP 4539396B2
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- JP
- Japan
- Prior art keywords
- terminal
- mounting
- semiconductor device
- measurement
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
図1は、本発明に基づく半導体装置の概略平面図(a)、及びA−A’線概略断面図(b)である。
プリント配線基板の規格が第1の実施の形態と同様であり、前記外部接続端子を80個配する場合、従来例によれば、図6(a)に示すように、半導体装置53のサイズは5.3mm×9.0mmとなった。これに対し、本実施の形態では、図2に示すように、実装用端子4を56個配置し、測定用端子5を24個配置した場合、半導体装置1のサイズは5.3mm×5.3mmとなる。
本発明に基づく半導体装置は、前記プリント配線基板に接続される。具体的には、図3に示すように、本発明に基づく半導体装置1の実装用端子4とプリント配線基板9のランド10とがはんだバンプ8によって接続され、本発明に基づく半導体装置1がプリント配線基板9に接続される。
5…測定用端子、6…樹脂、7a、7b…電極、8…はんだバンプ、
9…プリント配線基板、10…ランド
Claims (3)
- 半導体チップを再配線用のインターポーザーに接続してなる半導体装置として、
プリント配線基板との接続に用いられる実装用端子と、半導体チップの電気的テスト に用いられる測定用端子とからなる外部接続端子が前記インターポーザーの一方の面側 に設けられ、前記実装用端子が前記インターポーザーの周辺部に配され、前記測定用端 子の少なくとも一部が前記実装用端子の内側に前記実装用端子より狭ピッチ又は狭サイ ズの配列ピッチで配されている
半導体装置が、前記一方の面側にて前記実装用端子を介して前記プリント配線基板にはんだ接続され、前記プリント配線基板には、前記測定用端子が接続されないと共に測定用端子自体が設けられていない、実装構造。 - 前記測定用端子が前記半導体チップの存在領域内の前記インターポーザーの中央部に配されている、請求項1に記載した実装構造。
- 前記測定用端子にプローブが接触されて前記電気的テストが行われる、請求項1に記載した実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005090578A JP4539396B2 (ja) | 2005-03-28 | 2005-03-28 | 半導体装置の実装構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005090578A JP4539396B2 (ja) | 2005-03-28 | 2005-03-28 | 半導体装置の実装構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006278374A JP2006278374A (ja) | 2006-10-12 |
JP4539396B2 true JP4539396B2 (ja) | 2010-09-08 |
Family
ID=37212869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005090578A Expired - Fee Related JP4539396B2 (ja) | 2005-03-28 | 2005-03-28 | 半導体装置の実装構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4539396B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006344824A (ja) | 2005-06-09 | 2006-12-21 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2009182104A (ja) * | 2008-01-30 | 2009-08-13 | Toshiba Corp | 半導体パッケージ |
JP4343256B1 (ja) | 2008-07-10 | 2009-10-14 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN110473839A (zh) | 2018-05-11 | 2019-11-19 | 三星电子株式会社 | 半导体封装系统 |
US10991638B2 (en) | 2018-05-14 | 2021-04-27 | Samsung Electronics Co., Ltd. | Semiconductor package system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09307024A (ja) * | 1996-05-17 | 1997-11-28 | Matsushita Electron Corp | チップキャリア |
JP2004022664A (ja) * | 2002-06-13 | 2004-01-22 | Matsushita Electric Ind Co Ltd | 半導体装置のパッケージおよび検査回路 |
JP2004342947A (ja) * | 2003-05-19 | 2004-12-02 | Oki Electric Ind Co Ltd | 半導体パッケージ |
JP2005079144A (ja) * | 2003-08-28 | 2005-03-24 | Kyocera Corp | 多層配線基板およびプローブカード |
JP2005209882A (ja) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp | 半導体パッケージ及び半導体装置 |
-
2005
- 2005-03-28 JP JP2005090578A patent/JP4539396B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09307024A (ja) * | 1996-05-17 | 1997-11-28 | Matsushita Electron Corp | チップキャリア |
JP2004022664A (ja) * | 2002-06-13 | 2004-01-22 | Matsushita Electric Ind Co Ltd | 半導体装置のパッケージおよび検査回路 |
JP2004342947A (ja) * | 2003-05-19 | 2004-12-02 | Oki Electric Ind Co Ltd | 半導体パッケージ |
JP2005079144A (ja) * | 2003-08-28 | 2005-03-24 | Kyocera Corp | 多層配線基板およびプローブカード |
JP2005209882A (ja) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp | 半導体パッケージ及び半導体装置 |
Also Published As
Publication number | Publication date |
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JP2006278374A (ja) | 2006-10-12 |
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