JP5122812B2 - Pn接合を有するナノウィスカ及びその製造方法 - Google Patents
Pn接合を有するナノウィスカ及びその製造方法 Download PDFInfo
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- JP5122812B2 JP5122812B2 JP2006506067A JP2006506067A JP5122812B2 JP 5122812 B2 JP5122812 B2 JP 5122812B2 JP 2006506067 A JP2006506067 A JP 2006506067A JP 2006506067 A JP2006506067 A JP 2006506067A JP 5122812 B2 JP5122812 B2 JP 5122812B2
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- nanowhisker
- nanowhiskers
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- semiconductor material
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
- H01L29/885—Esaki diodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
Description
本出願は、2003年4月4日出願の米国仮特許出願(No.60/459,990)の優先権の利益を請求する、そして引用によってその仮出願の全てはここに組み入れられる。
(a) 基板に一次元のナノウィスカを形成するステップであって、そのナノウィスカは第1の材料で形成され、
(b) 基板に更なる材料の第1の層を少なくとも形成し、前記ナノエレメントを少なくとも部分的に囲むステップで、その更なる材料は第1の導電型のドーパント材料を有しており、
(c) 前記ドーパント材料がナノエレメントに拡散して、それによって所望の導電性を生成するように、その更なる材料を処理するステップとから成る方法を提供する。
少なくとも基板に形成され、ナノエレメントを少なくとも一部囲んだ第1の層とからなるナノ技術構造物であって、前記第1の層は、第1の導電型のドーパント材料を有しており、前記第1の導電型のドーパント材料がナノエレメントに拡散し、それによって前記ナノエレメント内に所望の導電性を生成するナノエレメント構造物を提供する。
(a)基板から直立したナノウィスカを作成し、
(b)基板に第1の層の材料を形成し、ナノウィスカを囲み部分的にそのナノウィスカの上方に広がり、またその第1の層は第1の導電型のドーパント材料を有し、
(c)前記第1の層の上に第2の層の材料を形成し、ナノウィスカを囲みそのナノウィスカの頂部に向かって広がり、またその第2の層は第2の導電型のドーパント材料を有し、その結果、前記第1と第2の層からそれぞれ前記ナノウィスカの第1と第2の領域に拡散させることにより、そのナノウィスカ内で第1と第2の領域間にPN接合を生成する方法を提供する。
(a)第1の半導体結晶材料の第1のセグメントと、第1のセグメントのそれとは異なる第2の半導体結晶材料の第2のセグメントとを有し、これによって第1と第2のセグメント間にヘテロ接合を形成する一次元ナノエレメントを形成し、
(b)相反する導電型の電荷キャリアをヘテロ接合の対向する面に付与して、所定の特性、これはフェルミ準位のピンニングよって少なくとも部分的に決定されるが、そのような特性を有するPN接合を生成するように、前記第1と第2の材料が選択される、方法を提供する。
Claims (10)
- 第1の半導体材料のナノウィスカ(74)と、
前記ナノウィスカをその全長の少なくとも一部に沿って囲みかつこれと接触している、少なくとも一つの第2の半導体材料のエンクロージャ(76)とからなる、構造物であって、
前記第1と第2の半導体材料は、互いに異なり、前記ナノウィスカ(74)とエンクロージャ(76)との間にPN接合を生成するために互いに反対の導電型の電荷キャリアを与え、
前記エンクロージャ(76)はバルク成長した層であり、前記ナノウィスカ(74)を埋め込んでいることを特徴とする、構造物。 - 前記ナノウィスカ(74)は、基板(70)から直立したことを特徴とする請求項1に記載の構造物。
- 前記ナノウィスカ(74)は、少なくとも該ナノウィスカの最外表面が、第1の導電型であることを特徴とする、請求項1又は2に記載の構造物。
- 前記第1の半導体材料は、第1のバンドギャップを有するIII−V族化合物であり、前記第2の半導体材料は、第1のバンドギャップとは異なる第2のバンドギャップを有するIII−V族化合物であることを特徴とする、請求項1に記載の構造物。
- 前記エンクロージャ(76)は、前記ナノウィスカ(74)からその周りに該ナノウィスカを取り囲んでバルク成長した層であることを特徴とする、請求項1に記載の構造物。
- ナノウィスカ(74)と前記ナノウィスカをその全長の少なくとも一部に沿って囲みかつこれと接触しているエンクロージャ(76)とからなる構造物を形成する方法であって、該方法は、
触媒成長によって、第1の導電型を有する第1の半導体材料のナノウィスカ(74)を形成するステップと、
バルク成長によって、前記ナノウィスカ(74)上に、前記第1の半導体材料とは互いに異なりかつ前記第1の導電型とは反対の第2の導電型を有する第2の半導体材料のエンクロージャを成長させるステップとを有し、
これにより、前記ナノウィスカ(74)の第1の半導体材料と前記エンクロージャ(76)の第2の半導体材料との間にPN接合が形成されることを特徴とする、方法。 - 前記エンクロージャ(76)の成長は、バルク成長を支えるべく温度と圧力との少なくとも一方を調整することを含むことを特徴とする、請求項6に記載の方法。
- 前記エンクロージャ(76)の成長は、そのエンクロージャの成長の前に、ナノウィスカ(74)上にある触媒の粒子を除去することを含むことを特徴とする、請求項6に記載の方法。
- 前記ナノウィスカ(74)は、化学ビームエピタキシによって成長されることを特徴とする請求項6に記載の方法。
- 前記ナノウィスカ(74)は、III族を強化した条件の下に生成してそのナノウィスカの表面に余剰のIII族原子を生成するIII-V族化合物を含むことを特徴とする請求項6に記載の方法。
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US7910492B2 (en) | 2011-03-22 |
KR101064318B1 (ko) | 2011-09-14 |
CN1826694B (zh) | 2012-04-25 |
US20050006673A1 (en) | 2005-01-13 |
CN1826694A (zh) | 2006-08-30 |
US20110193055A1 (en) | 2011-08-11 |
CA2521498A1 (en) | 2004-10-14 |
US8242481B2 (en) | 2012-08-14 |
CA2521498C (en) | 2012-06-05 |
WO2004088755A1 (en) | 2004-10-14 |
US7432522B2 (en) | 2008-10-07 |
EP1634334A1 (en) | 2006-03-15 |
US20090014711A1 (en) | 2009-01-15 |
WO2004088755A8 (en) | 2005-08-18 |
JP2006522472A (ja) | 2006-09-28 |
US8120009B2 (en) | 2012-02-21 |
US20120126200A1 (en) | 2012-05-24 |
KR20050118229A (ko) | 2005-12-15 |
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