WO2002001648A1

WO2002001648A1 - Semiconductor structure, device, circuit, and process

Info

Publication number: WO2002001648A1
Application number: PCT/US2001/018612
Authority: WO
Inventors: Jamal Ramdani; Lyndee Hilt; William J. Ooms
Original assignee: Motorola, Inc.
Priority date: 2000-06-28
Filing date: 2001-06-07
Publication date: 2002-01-03
Also published as: AU2001271293A1; TW495996B

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24). The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer (26). Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Description

SEMICONDUCTOR STRUCTURE, DEVICE, CIRCUIT, AND PROCESS

Field of the Invention

This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to compound semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline compound semiconductor material.

Background of the Invention

The vast majority of semiconductor discrete devices and integrated circuits are fabricated from silicon, at least in part because of the availability of inexpensive, high quality monocrystalline silicon substrates. Other semiconductor materials, such as the so called compound semiconductor materials, have physical attributes, including wider bandgap and/or higher mobility than silicon, or direct bandgaps that makes these materials advantageous for certain types of semiconductor devices. Unfortunately, compound semiconductor materials are generally much more expensive than silicon and are not available in large wafers as is silicon. Gallium arsenide (GaAs), the most readily available compound semiconductor material, is available in wafers only up to about 150 millimeters (mm) in diameter. In contrast, silicon wafers are available up to about 300 mm and are widely available at 200 mm. The 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than

GaAs.

Because of the desirable characteristics of compound semiconductor materials, and because of their present generally high cost and low availability in bulk form, for many years attempts have been made to grow thin films of the compound semiconductor materials on a foreign substrate. To achieve optimal characteristics of the compound semiconductor material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline compound semiconductor material on germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of compound semiconductor material to be of low crystalline quality.

If a large area thin film of high quality monocrystalline compound semiconductor material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of compound semiconductor material or in an epitaxial film of such material on a bulk wafer of compound semiconductor material. In addition, if a thin film of high quality monocrystalline compound semiconductor material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the compound semiconductor material.

Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline compound semiconductor film over another monocrystalline material and for a process for making such a structure.

Brief Description of the Drawings

The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which: FIGS. 1, 2, 3, 9, 10 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;

FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer;

FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer;

FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer; FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer;

FIG. 11 includes an illustration of a block diagram of a portion of a communicating device; FIGS. 12-16 include illustrations of cross-sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion; and

FIGS. 17-23 include illustrations of cross-sectional views of a portion of another integrated circuit that includes a semiconductor laser and an MOS transistor.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description of the Drawings

FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.

In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and compound semiconductor layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the compound semiconductor layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.

Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.

Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material. For example, the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied semiconductor material. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.

The compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II(A or B) and VIA elements (II- VI semiconductor compounds), and mixed II- VI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.

FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of compound semiconductor material. The additional buffer layer, formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer.

FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.

As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing~e.g., compound semiconductor layer 26 formation. The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline compound semiconductor layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline compound semiconductor layers because it allows any strain in layer 26 to relax. Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32. For example, layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.

In accordance with one embodiment of the present invention, semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound. In accordance with another embodiment of the invention, semiconductor layer

38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36. The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

Example 1

In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr_zBa_μzTiO₃ where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO_x) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm. In accordance with this embodiment of the invention, compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1- 10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers of Ti-As or Sr-Ga-O have been shown to successfully grow GaAs layers.

Example 2 In accordance with a further embodiment of the invention, monocrystalline substrate 22 is a silicon substrate as described above. The accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer. The accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO₃, BaZrO₃, SrHfO₃, BaSnO₃ or BaHfO₃. For example, a monocrystalline oxide layer of BaZrO₃ can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.

An accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials in the indium phosphide (InP) system. The compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGalnAsP), having a thickness of about 1.0 nm to 10 μm. A suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As), zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P), strontium-oxygen-arsenic (Sr-O-As), strontium-oxygen-phosphorus (Sr-O-P), barium-oxygen-arsenic (Ba-O-As), indium- strontium-oxygen (In-Sr-O), or barium-oxygen-phosphorus (Ba-O-P), and preferably 1- 2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template. A monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer. The resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.

Example 3

In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a II- VI material overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr^Ba^TiO^ where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The II- VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe). A suitable template for this material system includes 1- 10 monolayers of zinc-oxygen (Zn-O) followed by 1 -2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.

Example 4

This embodiment of the invention is an example of structure 40 illustrated in FIG. 2. Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAsJPj._x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an In_yGaj._yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material. The compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.

Example 5

This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, a buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline compound semiconductor material layer. The buffer layer, a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs). In accordance with one aspect of this embodiment, buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. The buffer layer preferably has a thickness of about 10-30 nm. Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.

Example 6

This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalling compound semiconductor material layer 26 may be the same as those described above in connection with example 1.

Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above). For example, amorphous layer 36 may include a combination of SiO_x and Sr_zBa,._z TiO₃ (where z ranges from 0 to 1), which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.

The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.

Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.

Referring again to FIGS. 1 - 3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.

FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.

In accordance with one embodiment of the invention, substrate 22 is a (100) or (H I) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable. Still referring to FIGS. 1 - 3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. If the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline Sr_xBa₁._xTiO₃, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline compound semiconductor layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline compound semiconductor layer can thereby be achieved. The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1 - 3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 0.5° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process- is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.

In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch' in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.

After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material.

For the subsequent growth of a layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.

FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention. Single crystal SrTiO₃ accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.

FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.

The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The buffer layer is formed overlying the template layer before the deposition of the monocrystalline compound semiconductor layer. If the buffer layer is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.

Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.

In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 1 to about 10 minutes.

However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.

For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38. As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.

FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal

SrTiO₃ accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.

FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.

The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other III-V and II- VI monocrystalline compound semiconductor layers can be deposited overlying the monocrystalline oxide accommodating buffer layer. Each of the variations of compound semiconductor materials and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the compound semiconductor layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a compound semiconductor material layer comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.

FIG. 9 illustrates schematically, in cross section, a device structure 50 in accordance with a further embodiment of the invention. Device structure 50 includes a monocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer.

Monocrystalline semiconductor substrate 52 includes two regions, 53 and 54. An electrical semiconductor component generally indicated by the dashed line 56 is formed, at least partially, in region 53. Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit. For example, electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited. The electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry. A layer of insulating material 58 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 56.

Insulating material 58 and any other layers that may have been formed or deposited during the processing of semiconductor component 56 in region 53 are removed from the surface of region 54 to provide a bare silicon surface in that region. As is well known, bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface. A layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 54 and is reacted with the oxidized surface to form a first template layer (not shown). In accordance with one embodiment of the invention a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer. Initially during the deposition the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form the monocrystalline barium titanate layer. The partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer. The oxygen diffusing through the barium titanate reacts with silicon at the surface of region 54 to form an amorphous layer of silicon oxide on the second region and at the interface between the silicon substrate and the monocrystalline oxide. In accordance with an embodiment of the invention, the step of depositing the monocrystalline oxide layer is terminated by depositing a second template layer 60, which can be 1-10 monolayers of titanium, barium, strontium, barium and oxygen, titanium and oxygen, or strontium and oxygen. A layer 64 of a monocrystalline semiconductor material is then deposited overlying the second template layer by a process of molecular beam epitaxy. The deposition of layer 64 may be initiated by depositing a layer of arsenic onto the template. This initial step is followed by depositing gallium and arsenic to form monocrystalline gallium arsenide.

In accordance with one aspect of the present embodiment, after semiconductor layer 60 formation, the monocrystalline titanate layer and the silicon oxide layer, which is interposed between substrate 52 and the titanate layer, are exposed to an anneal process such that the titanate and oxide layers form an amorphous oxide layer 62. An additional compound semiconductor layer 66 is then epitaxially grown over layer 64, using the techniques described above in connection with layer 64, to form compound semiconductor layer 67. Alternatively, the above described anneal process can be performed after formation of additional compound semiconductor layer 66.

In accordance with a further embodiment of the invention, a semiconductor component, generally indicated by a dashed line 68 is formed, at least partially, in compound semiconductor layer 66. Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III- V compound semiconductor material devices. Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, an electromagnetic radiation (e.g., light—infra red to ultra violet radiation) emitting device, an electromagnetic radiation detector such as a photodetector, a heteroj unction bipolar transistor (HBT), a high frequency MESFET, or another component that utilizes and takes advantage of the physical properties of compound semiconductor materials. A metallic conductor schematically indicated by the line 70 can be formed to electrically couple device 68 and device 56, thus implementing an integrated device that includes at least one component formed in the silicon substrate and one device formed in the monocrystalline compound semiconductor material layer. Although illustrative structure 50 has been described as a structure formed on a silicon substrate 52 and having a barium (or strontium) titanate layer and a gallium arsenide layer 66, similar devices can be fabricated using other monocrystalline substrates, oxide layers and other monocrystalline compound semiconductor layers as described elsewhere in this disclosure. FIG. 10 illustrates a semiconductor structure 72 in accordance with a further embodiment of the invention. Structure 72 includes a monocrystalline semiconductor substrate 74 such as a monocrystalline silicon wafer that includes a region 75 and a region 76. An electrical component schematically illustrated by the dashed line 78 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry. Using process steps similar to those described above, a monocrystalline oxide layer and an intermediate amorphous silicon oxide layer are formed overlying region 76 of substrate 74. A template layer 80 and subsequently a monocrystalline semiconductor layer 82 are formed overlying the monocrystalline oxide layer. An amorphous oxide layer 84 is then formed by exposing the monocrystalline oxide and silicon oxide films to an anneal process. In accordance with a further embodiment of the invention, an additional monocrystalline oxide layer 86 is formed overlying layer 82 by process steps similar to those used to form the monocrystalling oxide material described above, and an additional monocrystalline semiconductor layer 90 is formed overlying monocrystalline oxide layer 86 by process steps similar to those used to form layer 82. Monocrystalline oxide layer 86 may desirably be exposed to an additional anneal process to cause the material to become amorphous. However, in accordance with various aspects of this embodiment, layer 86 retains its monocrystalline form. In accordance with one embodiment of the invention, at least one of layers 82 and 90 are formed from a compound semiconductor material. A semiconductor component generally indicated by a dashed line 92 is formed at least partially in monocrystalline semiconductor layer 82. In accordance with one embodiment of the invention, semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, by monocrystalline oxide layer 86. In addition, monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor. In accordance with one embodiment of the invention, monocrystalline semiconductor layer 82 is formed from a group III-V compound and semiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials. In accordance with yet a further embodiment of the invention, an electrical interconnection schematically illustrated by the line 94 electrically interconnects component 78 and component 92. Structure 72 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials.

By way of more specific examples, other integrated circuits and systems are illustrated in FIGS. 11-23. FIG. 11 includes a simplified block diagram illustrating a portion of a communicating device 100 having a signal transceiving means 101 , an integrated circuit 102, an output unit 103, and an input unit 104. Examples of the signal transceiving means include an antenna, a modem, or any other means by which information or data can be sent either to or from an external unit. As used herein, transceiving is used to denote that the signal transceiving means may be capable of only receiving, only transmitting, or both receiving and transmitting signals from or to the communicating device. The output unit 103 can include a display, a monitor, a speaker, or the like. The input unit can include a microphone, a keyboard, or the like. Note that in alternative embodiments the output unit 103 and input unit 104 could be replaced by a single unit such as a memory, or the like. The memory can include random access memory or nonvolatile memory, such as a hard disk, a flash memory card or module, or the like.

An integrated circuit is generally a combination of at least two circuit elements (e.g., transistors, diodes, resistors, capacitors, and the like) inseparably associated on or within a continuous substrate. The integrated circuit 102 includes a compound semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026. The compound semiconductor portion 1022 includes electrical components that are formed at least partially within a compound semiconductor material. Transistors and other electrical components within the compound semiconductor portion 1022 are capable of processing signals at radio frequencies of at least approximately 0.8 GHz. In other embodiments, the signals could be at lower or higher frequencies. For example, some materials, such as indium gallium arsenide, are capable of processing signals at radio frequency signals at approximately 27 GHz.

The compound semiconductor portion 1022 further includes a duplexer 10222, a radio frequency-to-baseband converter 10224 (demodulating means or demodulating circuit), baseband-to-radio frequency converter 10226 (modulating means or modulating circuit), a power amplifier 10228, and an isolator 10229. The bipolar portion 1024 and the MOS portion 1026 typically are formed in a Group IV semiconductive material. The bipolar portion 1024 includes a receiving amplifier 10242, an analog-to-digital converter 10244, a digital-to-analog converter 10246, and a transmitting amplifier 10248. The MOS portion 1026 includes a digital signal processing means 10262. An example of such means includes any one of the commonly available DSP cores available in the market, such as the Motorola DSP 566xx (from Motorola, Incorporated of Schaumburg, Illinois) and Texas Instruments TMS 320C54x (from Texas Instruments of Dallas, Texas) families of digital signal processors. This digital signal processing means 10262 typically includes complementary MOS (CMOS) transistors and analog-to-digital and digital-to-analog converters. Clearly, other electrical components are present in the integrated circuit 102. In one mode of operation, the communicating device 100 receives a signal from an antenna, which is part of the signal transceiving means 101. The signal passes through the duplexer 10222 to the radio frequency-to-baseband converter 10224. The analog data or other information is amplified by receiving amplifier 10224 and transmitted to the digital signal processing means 10262. After the digital signal processing means 10262 has processed the information or other data, the processed information or other data is transmitted to the output unit 103. If the communicating device is a pager, the output unit can be a display. If the communicating device is a cellular telephone, the output unit 103 can include a speaker, a display, or both.

Data or other information can be sent through the communicating device 100 in the opposite direction. The data or other information will come in through the input unit 104. In a cellular telephone, this could include a microphone or a keypad. The information or other data is then processed using the digital signal processing means 10262. After processing, the signal is then converted using the digital-to-analog converter 10246. The converted signal is amplified by the transmitting amplifier 10248. The amplified signal is modulated by the baseband-to-radio frequency converter 10226 and further amplified by power amplifier 10228. The amplified RF signal passes through the isolator 10229 and duplexer 10222 to the antenna.

Prior art embodiments of the communicating device 100 would have at least two separate integrated circuits: one for the compound semiconductor portion 1022 and one for the MOS portion 1026. The bipolar portion 1024 may be on the same integrated circuit as the MOS portion 1026 or could be on still another integrated circuit. With an embodiment of the present invention, all three portions can now be formed within a single integrated circuit. Because all of the transistors can reside on a single integrated circuit, the communicating device can be greatly miniaturized and allow for greater portability of a communicating device.

Attention is now directed to a method for forming exemplary portions of the integrated circuit 102 as illustrated in FIGS. 12-16. In FIG. 12, a p-type doped, monocrystalline silicon substrate 110 is provided having a compound semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026. Within the bipolar portion, the monocrystalline silicon substrate is doped to form an N⁺ buried region

1102. A lightly p-type doped epitaxial monocrystalline silicon layer 1104 is then formed over the buried region 1102 and the substrate 110. A doping step is then performed to create a lightly n-type doped drift region 1117 above the N⁺ buried region 1102. The doping step converts the dopant type of the lightly p-type epitaxial layer within a section of the bipolar region 1024 to a lightly doped n-type monocrystalline silicon region. A field isolation region 1106 is then formed between the bipolar portion 1024 and the MOS portion 1026. A gate dielectric layer 1110 is formed over a portion of the epitaxial layer 1104 within MOS portion 1026, and the gate electrode 1112 is then formed over the gate dielectric layer 1110. Sidewall spacers 1115 are formed along vertical sides of the gate electrode 1112 and gate dielectric layer 1110. A p-type dopant is introduced into the drift region 1117 to form an active or intrinsic base region 1114. An n-type, deep collector region 1108 is then formed within the bipolar portion 1024 to allow electrical connection to the buried region 1102. Selective n-type doping is performed to form N⁺ doped regions 1116 and the emitter region 1120. N⁺ doped regions 1116 are formed within layer 1104 along adjacent sides of the gate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor. The N⁺ doped regions 1116 and emitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed. A p-type doped region is formed to create the inactive or extrinsic base region 1118 which is a P⁺ doped region (doping concentration of at least 1 E 19 atoms per cubic centimeter).

In the embodiment described, several processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers. The formation of the device up to this point in the process is performed using conventional steps. . As illustrated, a standard N-channel MOS transistor has been formed within the MOS region 1026, and a vertical NPN bipolar transistor has been formed within the bipolar portion 1024. As of this point, no circuitry has been formed within the compound semiconductor portion 1022.

All of the layers that have been formed during the processing of the bipolar and MOS portions of the integrated circuit are now removed from the surface of compound semiconductor portion 1022. A bare silicon surface is thus provided for the subsequent processing of this portion, for example in the manner set forth above. An accommodating buffer layer 124 is then formed over the substrate 110 as illustrated in FIG. 13. The accommodating buffer layer will initially form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface in portion 1022 and will eventually form an amorphous oxide layer as described herein. The portion of layer 124 that forms over portions 1024 and 1026, however, may be polycrystalline or amorphous because it is formed over a material that is not monocrystalline, and therefore, does not nucleate monocrystalline growth. The accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers. In one particular embodiment, the accommodating buffer layer is approximately 5-15 nm thick. During the formation of the accommodating buffer layer, an amorphous intermediate layer 122 is formed along the uppermost silicon surfaces of the integrated circuit 102. This amorphous intermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm. Following the formation of the accommodating buffer layer 124 and the amorphous intermediate layer 122, a template layer 126 is then formed and has a thickness in a range of approximately one to ten monolayers of a material. In one particular embodiment, the material includes titanium-arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGS. 1 - 3 and 5 - 10. A monocrystalline compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 as shown in FIG. 14. The portion of layer 132 that is grown over portions of layer 124 that are not monocrystalline may be polycrystalline or amorphous. The monocrystalline compound semiconductor layer can be formed by a number of methods and typically includes a material such as germanium, gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compounds semiconductor materials as previously mentioned. The thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-500 nm. In this particular embodiment, each of the elements within the template layer are also present in the accommodating buffer layer 124, the monocrystalline compound semiconductor material 132, or both. Therefore, the delineation between the template layer 126 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between the accommodating buffer layer 124 and the monocrystalline compound semiconductor layer 132 is seen. Next, an amorphous oxide layer 125 is formed by exposing amorphous oxide layer 122 and accommodating buffer layer 124 to an anneal process. Either before or after the anneal process, additional semiconductor material can be deposited onto compound semiconductor layer 132 to form compound semiconductor layer 133, as illustrated in FIG. 15. At this point in time, sections of the compound semiconductor layer 133 and amorphous oxide layer 125 are removed from portions overlying the bipolar portion 1024 and the MOS portion 1026. In accordance with an alternate aspect of this embodiment, the anneal process may suitably be performed after portions of layers 122 and/or 124 have been removed. After the sections are removed, an insulating layer 142 is then formed over the substrate 110. The insulating layer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5. After the insulating layer 142 has been deposited, it is then polished, removing portions of the insulating layer 142 that overlie monocrystalline compound semiconductor layer 133.

A transistor 144 is then formed within the monocrystalline compound semiconductor portion 1022 by forming a gate electrode 148 on the monocrystalline compound semiconductor layer 133 and doped regions 146 within the monocrystalline compound semiconductor layer 133. In this embodiment, the transistor 144 is a metal- semiconductor field-effect transistor (MESFET). If the MESFET is an n-type

MESFET, the doped regions 146 and monocrystalline compound semiconductor layer 133 are also n-type doped. If a p-type MESFET were to be formed, then the doped regions 146 and monocrystalline compound semiconductor layer 133. would have just the opposite doping type. The heavier doped (N⁺) regions 146 allow ohmic contacts to be made to the monocrystalline compound semiconductor layer 133. At this point in time, the active devices within the integrated circuit have been formed. This particular embodiment includes an n-type MESFET, a vertical NPN bipolar transistor, and a planar n-channel MOS transistor. Many other types of transistors, including P-channel MOS transistors, p-type vertical bipolar transistors, p-type MESFETs, and combinations of vertical and planar transistors, can be used. Also, other electrical components, such as resistors, capacitors, diodes, and the like, may be formed in one or more of the portions 1022, 1024, and 1026.

Processing continues to form a substantially completed integrated circuit 102 as illustrated in FIG. 16. An insulating layer 152 is formed over the substrate 110. The insulating layer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 16. A second insulating layer 154 is then formed over the first insulating layer 152. Portions of layers 154, 152, 142, and 125 are removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 154 to provide the lateral connections between the contacts. As illustrated in FIG. 16, interconnect 1562 connects a source or drain region of the n-type

MESFET within portion 1022 to the deep collector region 1108 of the NPN transistor within the bipolar portion 1024. The emitter region 1120 of the NPN transistor is connected to one of the doped regions 1116 of the n-channel MOS transistor within the MOS portion 1026 via an interconnect 1564. The other doped region 1116 is electrically connected to other portions of the integrated circuit that are not shown via an interconnect 1566.

A passivation layer 156 is formed over the interconnects 1562, 1564, and 1566 and insulating layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within the integrated circuit 102 but are not illustrated in the figures. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections between the various components within the integrated circuit 102.

As can be seen from the previous embodiment, active devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within bipolar portion into the compound semiconductor portion 1022 or the MOS portion 1024. More specifically, turning to the embodiment as described with respect to FIG. 11, the amplifiers 10248 and 10242 may be moved over to the compound semiconductor portion 1022, and the converters 10244 and 10246 can be moved over into the MOS portion 1026. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit.

In still another embodiment, an integrated circuit can be formed such that it includes an optical laser in a compound semiconductor portion and an optical interconnect (waveguide) to an MOS transistor within a Group IV semiconductor region of the same integrated circuit. FIGS. 17 - 23 include illustrations of one embodiment.

FIG. 17 includes an illustration of a cross-section view of a portion of an integrated circuit 160 that includes a monocrystalline silicon wafer 161. An amorphous layer 164, similar to that previously described, has been formed over wafer 161. In this specific embodiment, the layers needed to form the optical laser will be formed first, followed by the layers needed for the MOS transistor. In FIG. 17, the lower mirror layer 166 includes alternating layers of compound semiconductor materials. For example, the first, third, and fifth films within the optical laser may include a material such as gallium arsenide, and the second, fourth, and sixth films within the lower mirror layer 166 may include aluminum gallium arsenide or vice versa. Layer 168 includes the active region that will be used for photon generation. Upper mirror layer 170 is formed in a similar manner to the lower mirror layer 166 and includes alternating films of compound semiconductor materials. In one particular embodiment, the upper mirror layer 170 may be p-type doped compound semiconductor materials, and the lower mirror layer 166 may be n-type doped compound semiconductor materials. An accommodating buffer layer 172, which may be formed of materials chemically similar to the monocrystalline oxide materials used to form layer 164, is formed over the upper mirror layer 170. In an alternative embodiment, amorphous oxide layer 164 and accommodating buffer layer 172 may be formed from chemically different materials. Both layers 164 and 172, however, function essentially the same in that each is used for making a transition between a compound semiconductor layer and a monocrystalline Group IV semiconductor layer. A monocrystalline Group IV semiconductor layer 174 is formed over the accommodating buffer layer 172. In one particular embodiment, the monocrystalline Group IV semiconductor layer 174 includes germanium, silicon germanium, silicon germanium carbide, or the like. In FIG. 18, the MOS portion is processed to form electrical components within this upper monocrystalline Group IV semiconductor layer 174. As illustrated in FIG. 18, a field isolation region 171 is formed from a portion of layer 174. A gate dielectric layer 173 is formed over the layer 174, and a gate electrode 175 is formed over the gate dielectric layer 173. Doped regions 177 are source, drain, or source/drain regions for the transistor 181 , as shown. Sidewall spacers 179 are formed adjacent to the vertical sides of the gate electrode 175. Other components can be made within at least a part of layer 174. These other components include other transistors (n-channel or p-channel), capacitors, transistors, diodes, and the like.

A monocrystalline Group IV semiconductor layer is epitaxially grown over one of the doped regions 177. An upper portion 184 is P+ doped, and a lower portion 182 remains substantially intrinsic (undoped) as illustrated in FIG. 18. The layer can be formed using a selective epitaxial process. In one embodiment, an insulating layer (not shown) is formed over the transistor 181 and the field isolation region 171. The insulating layer is patterned to define an opening that exposes one of the doped regions 177. At least initially, the selective epitaxial layer is formed without dopants. The entire selective epitaxial layer may be intrinsic, or a p-type dopant can be added near the end of the formation of the selective epitaxial layer. If the selective epitaxial layer is intrinsic, as formed, a doping step may be formed by implantation or by furnace doping. Regardless how the P+ upper portion 184 is formed, the insulating layer is then removed to form the resulting structure shown in FIG. 18. The next set of steps is performed to define the optical laser 180 as illustrated in FIG. 19. The field isolation region 171 and the accommodating buffer layer 172 are removed over the compound semiconductor portion of the integrated circuit. Additional steps are performed to define the upper mirror layer 170 and active layer 168 of the optical laser 180. The sides of the upper mirror layer 170 and active layer 168 are substantially coterminous.

Contacts 186 and 188 are formed for making electrical contact to the upper mirror layer 170 and the lower mirror layer 166, respectively, as shown in FIG. 19. Contact 186 has an annular shape to allow light (photons) to pass out of the upper mirror layer 170 into a subsequently formed optical waveguide.

An insulating layer 190 is then formed and patterned to define optical openings 192 extending to the upper mirror 170 and to one of the doped regions 184 as shown in FIG. 20. The insulating material can be any number of different materials, including an oxide, nitride, oxynitride, low-k dielectric, or any combination thereof. After defining openings 192, a higher refractive index material 202 is then formed overlying layer 190 and filling opening 192, as illustrated in FIG. 21. With respect to the higher refractive index material 202, "higher" is in relation to the material of the insulating layer 190 (i.e., material 202 has a higher refractive index compared to the insulating layer 190). Optionally, a relatively thin lower refractive index film (not shown) could be formed before forming the higher refractive index material 202. A hard mask layer 204 is then formed over the high refractive index layer 202. Portions of the hard mask layer 204 and high refractive index layer 202 are removed from portions overlying the opening and to areas closer to the sides of the structure illustrated in FIG. 21.

The balance of the formation of the optical waveguide, which is an optical interconnect, is completed as illustrated in FIG. 22. A deposition procedure (possibly a dep-etch process) is performed to effectively create sidewalls sections 212. In this embodiment, the sidewall sections 212 are made of the same material as material 202. The hard mask layer 204 is then removed, and a low refractive index layer 214 (low relative to material 202 and layer 212) is formed over the higher refractive index material 212 and 202 and exposed portions of the insulating layer 190. The dash lines in FIG. 22 illustrate the border between the high refractive index materials 202 and 212. This designation is used to identify that both are made of the same material but are formed at different times.

Processing is continued to form a substantially completed integrated circuit as illustrated in FIG. 23. A passivation layer 220 is then formed over the optical laser 180 and MOSFET transistor 181. Although not shown, other electrical or optical connections are made to the components within the integrated circuit but are not illustrated in FIG. 23. These interconnects can include other optical waveguides or may include metallic interconnects. In other embodiments, other types of lasers can be formed. For example, another type of laser can emit light (photons) horizontally instead of vertically. If light is emitted horizontally, the MOSFET transistor could be formed within the substrate 161, and the optical waveguide would be reconfigured, so that the laser is properly coupled (optically connected) to the transistor. In one specific embodiment, the optical waveguide can include at least a portion of monocrystalline oxide 168. Other configurations are possible.

Clearly, these embodiments of integrated circuits having compound semiconductor portions and Group IV semiconductor portions, are meant to illustrate embodiments of the present invention and not limit the present invention. There are multiplicity of other combinations and other embodiments of the present invention. For example, the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like, and the Group IV semiconductor can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits. By using embodiments of the present invention, it is how simpler to integrate devices that work better in compound semiconductor materials with other components that work better or are easily and/or inexpensively formed within Group IV semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase.

Although not illustrated, a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer. In this manner, the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II- VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.

By the use of this type of substrate, a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor device should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile conventional compound semiconductor wafers.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A semiconductor structure comprising:

a monocrystalline Group IV substrate;

an amorphous oxide layer formed on the substrate; and

a monocrystalline compound semiconductor material of first type formed overlying the amorphous oxide material.

2. The semiconductor structure of claim 1 further comprising a template layer formed between the amorphous oxide material and the monocrystalline compound semiconductor material of first type.

3. The semiconductor structure of claim 1 further comprising a buffer layer of monocrystalline semiconductor material of second type formed between the amorphous oxide material and the monocrystalline compound semiconductor material of first type.

4. The semiconductor structure of claim 3 further comprising a template layer formed between the amorphous oxide material and the buffer layer of monocrystalline semiconductor material of second type.

5. The semiconductor structure of claim 3 wherein the buffer layer comprises a monocrystalline semiconductor material selected from the group consisting of: germanium, and a superlattice of a material selected from GaAs_xP,__x where x ranges from 0 to 1,

where y ranges from 0 to 1, InGaAs, GaAs, AlGaAs, InGaP, AllnP, and AllnP.

6. The semiconductor structure of claim 1 wherein the amorphous oxide material comprises an oxide selected from the group consisting of alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafniates, alkaline earth metal tantalates, alkaline earth metal ruthenates, and alkaline earth metal niobates.

7. The semiconductor structure of claim 1 wherein the amorphous oxide material comprises Sr_xBaι__xTiO₃ where x ranges from 0 to 1.

8. The semiconductor structure of claim 1 wherein the amorphous oxide material comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.

9. The semiconductor structure of claim 8 wherein the monocrystalline Group IV substrate is characterized by a first lattice constant and the monocrystalline compound semiconductor material of first type is characterized by a second lattice constant different than the first lattice constant.

10. The semiconductor structure of claim 9 wherein the monocrystalline oxide is characterized by a third lattice constant different than the second lattice constant.

11. The semiconductor structure of claim 8 wherein the monocrystalline Group IV substrate is characterized by a first crystalline orientation and the monocrystalline oxide is characterized by a second crystalline orientation and wherein the second crystalline orientation is rotated with respect to the first crystalline orientation.

12. The semiconductor structure of claim 8 further comprising a second amorphous oxide layer formed between the Group IV substrate and the monocrystalline oxide.

13. The semiconductor structure of claim 12 wherein the Group IV substrate comprises silicon and the second amorphous oxide layer comprises a silicon oxide.

14. The semiconductor structure of claim 1 wherein the monocrystalline compound semiconductor material of first type comprises a material selected from the group consisting of: III-V compounds, mixed III-V compounds, II-VI compounds, and mixed II-VI compounds.

15. The semiconductor structure of claim 1 wherein the monocrystalline compound semiconductor material of first type comprises a material selected from the group consisting of: GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

16. The semiconductor structure of claim 1 further comprising an active device formed at least partially in the monocrystalline compound semiconductor material of first type.

17. The semiconductor structure of claim 1 wherein the amorphous oxide layer has a thickness of about 2 - 10 nm.

18. The semiconductor structure of claim 17 wherein the amorphous oxide layer has a thickness of about 5 - 6 nm.

19. The semiconductor structure of claim 1 further comprising a first active semiconductor device formed at least partially in the monocrystalline compound semiconductor layer.

20. The semiconductor structure of claim 19 wherein the first active semiconductor device comprises an optical device.

21. The semiconductor structure of claim 19 further comprising a second active semiconductor device formed at least partially in the monocrystalline semiconductor substrate.

22. The semiconductor structure of claim 21 further comprising an electrical connection coupling the first active semiconductor device and the second active semiconductor device.

23. A semiconductor structure comprising:

a monocrystalline semiconductor substrate;

a first amorphous layer overlying the monocrystalline semiconductor substrate;

a second amorphous oxide layer formed overlying the first amorphous layer; and

a monocrystalline compound semiconductor layer overlying the second amorphous oxide layer.

24. The semiconductor structure of claim 23 wherein the monocrystalline semiconductor substrate comprises a layer of a material comprising silicon.

25. The semiconductor structure of claim 24 wherein the first amorphous layer comprises a silicon oxide.

26. The semiconductor structure of claim 23 further comprising a template layer between the second amorphous oxide layer and the monocrystalline compound semiconductor layer.

27. The semiconductor structure of claim 26 further comprising a buffer layer between the template layer and the monocrystalline compound semiconductor layer.

28. The semiconductor structure of claim 27 wherein the second amorphous oxide layer comprises Sr_xBa_!.xTiO₃ where x ranges from 0 to 1.

29. The semiconductor structure of claim 19 wherein the first amorphous layer and the second amorphous oxide layer has a total thickness of about 2 - 10 nm.

30. The semiconductor structure of claim 29 wherein the first amorphous layer and the second amorphous oxide layer have a total thickness of about 5 - 6 nm.

31. The semiconductor structure of claim 23 further comprising a buffer layer between the second amorphous oxide layer and the monocrystalline compound semiconductor layer.

32. The semiconductor structure of claim 31 wherein the buffer layer comprises a layer of semiconductor material.

33. The semiconductor structure of claim 23 wherein the monocrystalline compound semiconductor material comprises a material selected from the group consisting of: GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS.

34. The semiconductor structure of claim 19 further comprising a first active semiconductor device formed at least partially in the monocrystalline compound semiconductor layer.

35. The semiconductor structure of claim 34 wherein the first active semiconductor device comprises an optical device.

36. The semiconductor structure of claim 34 further comprising a second active semiconductor device formed at least partially in the monocrystalline semiconductor substrate.

37. The semiconductor structure of claim 36 further comprising an electrical connection coupling the first active semiconductor device and the second active semiconductor device.

38. The semiconductor structure of claim 23 wherein the second amorphous oxide layer comprises an oxide selected from the group consisting of alkaline-earth-metal zirconates, and alkaline-earth-metal hafnates and the monocrystalline compound semiconductor layer comprises a material selected from the group consisting of: InP,

InGaAs, and InGaP.

39. The semiconductor structure of claim 23 wherein the monocrystalline substrate comprises a material comprising silicon, the second amorphous oxide layer comprises an alkaline-earth-metal titanate and the monocrystalline compound semiconductor material comprises a material selected from the group consisting of: GaAs, AlGaAs, ZnSe, and ZnSeS.

40. The semiconductor structure of claim 23 wherein the second amorphous oxide layer comprises an amorphous silicate.

41. The semiconductor structure of claim 40 wherein the amorphous oxide material comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.

42. The semiconductor structure of claim 23 wherein the amorphous oxide material comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.

43. A semiconductor structure comprising:

a first monocrystalline semiconductor substrate comprising silicon and having a first region and a second region;

a first amorphous oxide layer overlying the first region;

a second monocrystalline semiconductor layer overlying the first amorphous oxide layer;

a monocrystalline oxide layer overlying the second monocrystalline semiconductor layer; and

a third semiconductor layer overlying the monocrystalline oxide layer and wherein at least one of the second monocrystalline semiconductor layer and the third semiconductor layer comprises a compound semiconductor material.

44. The semiconductor structure of claim 43 wherein the first amorphous oxide layer comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.

45. The semiconductor structure of claim 43 wherein the amorphous oxide layer has a thickness of about 2 - 10 nm.

46. The semiconductor structure of claim 45 wherein the amorphous oxide layer has a thickness of about 5 - 6 nm.

47. The semiconductor structure of claim 43 further comprising a template layer between the first amorphous oxide layer and the second monocrystalline semiconductor layer.

48. The semiconductor structure of claim 43 further comprising an active semiconductor component positioned at least partially in the second monocrystalline semiconductor layer.

49. The semiconductor structure of claim 48 further comprising a second semiconductor component positioned at least partially in the second region of the first monocrystalline semiconductor substrate.

50. The semiconductor structure of claim 49 further comprising an electrical interconnection between the active semiconductor component and the second semiconductor component.

51. The semiconductor structure of claim 48 wherein the monocrystalline oxide layer comprises a gate dielectric of the active semiconductor component.

52. The semiconductor structure of claim 51 wherein the third semiconductor layer comprises a gate electrode.

53. The semiconductor structure of claim 51 wherein the monocrystalline oxide layer comprises an oxide selected from the group consisting of alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafniates, alkaline earth metal tantalates, alkaline earth metal ruthenates, and alkaline earth metal niobates.

54. The semiconductor structure of claim 48 wherein the second monocrystalline semiconductor layer comprises a group III-V compound and the active semiconductor component comprises a component in a radio frequency amplifier.

55. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline semiconductor substrate;

epitaxially growing a monocrystalline oxide layer overlying the monocrystalline semiconductor substrate;

forming a first amorphous oxide layer between the monocrystalline semiconductor substrate and the monocrystalline oxide layer during the step of epitaxially growing;

epitaxially growing a monocrystalline compound semiconductor layer overlying the monocrystalline oxide layer; and

thermally annealing the monocrystalline oxide layer to convert the monocrystalline oxide layer to a second amorphous oxide layer.

56. The process of claim 55 wherein the step of thermally annealing comprises the step of rapid thermal annealing.

57. The process of claim 56 wherein the step of rapid thermal annealing comprises rapid thermal annealing at a temperature between about 700° C and about 1000° C.

58. The process of claim 55 further comprising the step of forming a first template layer on the monocrystalline semiconductor substrate.

59. The process of claim 58 wherein the step of providing a monocrystalline semiconductor substrate comprises providing a substrate comprising silicon having a silicon oxide layer on a surface thereof and the step of forming a first template layer comprises the steps of: depositing a material from the group consisting of alkali earth metals and alkali earth metal oxides onto the silicon oxide layer and

heating the substrate to react the material with the silicon oxide.

60. The process of claim 59 wherein the alkali earth metals comprise an alkali earth metal from the group consisting of barium, strontium, and mixtures of barium and strontium, and the alkali earth metal oxides comprise an alkali earth metal oxide from the group consisting of barium oxide, strontium oxide, and barium strontium oxide.

61. The process of claim 51 wherein the step of epitaxially growing a monocrystalline oxide layer comprises the steps of:

heating the monocrystalline semiconductor substrate to a temperature between about 200°C and about 800°C; and

introducing reactants comprising strontium, titanium, and oxygen.

62. The process of claim 61 wherein the step of introducing comprises controlling the ratio of strontium to titanium and controlling partial pressure of oxygen.

63. The process of claim 62 wherein the step of oxidizing the monocrystalline semiconductor substrate comprises increasing the partial pressure of oxygen above a level necessary for epitaxially growing the monocrystalline oxide layer.

64. The process of claim 55 further comprising the step of forming a second template layer overlying the monocrystalline oxide layer.

65. The process of claim 64 wherein the step of forming a second template layer comprises the step of capping the monocrystalline oxide layer with a layer comprising a monolayer of a material selected from the group consisting of titanium, titanium and oxygen, strontium, and strontium and oxygen.

66. The process of claim 65 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises:

depositing a material from Group V on the second template layer; and

reacting the material from Group V with the material of the second template layer.

67. The process of claim 66 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer further comprises the steps of deposing a group III material and a Group V material to form a III-V compound semiconductor material after the step of reacting.

68. The process of claim 67 wherein the step of thermal annealing comprises the step of rapid thermal annealing the monocrystalline oxide layer after the step of epitaxially growing a monocrystalline compound semiconductor layer.

69. The process of claim 67 wherein the step of thermal annealing comprises the step of thermal annealing the monocrystalline oxide layer in the presence of an over pressure of the Group V material.

70. The process of claim 67 wherein the step of thermal annealing comprises heating the monocrystalline oxide layer at a temperature selected so as not to degrade the III-V compound semiconductor material.

71. The process of claim 65 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises:

depositing a material from Group III on the second template layer; and

reacting the material from Group III with the material of the second template layer.

72. The process of claim 71 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer further comprises the steps of deposing a group III material and a Group V material to form a III-V compound semiconductor material after the step of reacting.

73. The process of claim 72 wherein the step of thermal annealing comprises the step of rapid thermal annealing the monocrystalline oxide layer after the step of epitaxially growing a monocrystalline compound semiconductor layer.

74. The process of claim 72 wherein the step of thermal annealing comprises the step of thermal annealing the monocrystalline oxide layer in the presence of an over pressure of arsenic.

75. The process of claim 72 wherein the step of thermal annealing comprises heating the monocrystalline oxide layer at a temperature selected so as not to degrade the III-V compound semiconductor material.

76. The process of claim 65 further comprising the step of forming a buffer layer overlying the second template layer.

77. The process of claim 55 further comprising the step of forming a buffer layer overlying the monocrystalline oxide layer.

78. The process of claim 77 wherein the process of forming a buffer layer comprises the step of epitaxially depositing a layer of germanium overlying the monocrystalline oxide layer.

79. The process of claim 77 wherein the process of forming a buffer layer comprises the step of depositing a superlattice comprising a III-V group compound semiconductor material.

80. The process of claim 55 wherein the step of epitaxially growing a monocrystalline oxide layer comprises the step of epitaxially growing an oxide from the group consisting of the alkaline-earth-metal zirconates and the alkaline-earth-metal hafnates.

81. The process of claim 80 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises the step of epitaxially growing a monocrystalline layer of compound semiconductor material selected from the group consisting of InP AlInAs, AlGalnAsP, and InGaAs.

82. The process of claim 81 further comprising the step of forming a second template layer overlying the monocrystalline oxide layer by depositing a layer having a thickness of about 1-10 monolayers of a material M-N or M-O-N wherein M is selected from the group consisting of Zr, Hf, Sr, and Ba and N is selected from the group consisting of As, P, Ga, Al, and In.

83. The process of claim 55 wherein the step of epitaxially growing a monocrystalline oxide layer comprises the step of epitaxially growing an alkaline earth metal titanate.

84. The process of claim 83 wherein the step of epitaxially growing a moncrystalline compound semiconductor layer comprises the step of epitaxially growing a layer selected from the group consisting of GaAs, AlGaAs, ZnSe, and ZnSSe.

85. The process of claim 55 further comprising the step of forming an active semiconductor device at least partially in the monocrystalline compound semiconductor layer.

86. The process of claim 55 further comprising the step of epitaxially growing a second monocrystalline compound semiconductor layer on the monocrystalline compound semiconductor layer.

87. The process of claim 86 wherein the second monocrystalline compound semiconductor layer has a different composition than the monocrystalline compound semiconductor layer.

88. The process of claim 86 wherein the step of thermally annealing is performed after the step of epitaxially growing a second monocrystalline compound semiconductor layer.

89. The process of claim 86 wherein the step of thermally annealing is performed before the step of epitaxially growing a second monocrystalline compound semiconductor layer.

90. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline oxide layer having a surface;

forming a template layer on the surface;

epitaxially growing a monocrystalline compound semiconductor layer overlying the template; and

thermally annealing the monocrystalline oxide layer to convert the monocrystalline oxide layer to an amorphous oxide layer.

91. The process of claim 90 wherein the step of providing a monocrystalline oxide layer comprises providing a monocrystalline oxide layer comprising a material selected from the group consisting of alkaline-earth-metal titanates, alkaline-earth-metal zirconates, and alkaline-earth-metal hafnates.

92. The process of claim 90 wherein the step of providing a monocrystalline oxide layer comprises epitaxially growing a monocrystalline oxide layer lattice matched to an underlying monocrystalline silicon substrate.

93. The process of claim 92 wherein the step of epitaxially growing a monocrystalline oxide layer comprises growing a monocrystalline oxide layer having a thickness of about 2 - 10 nm.

94. The process of claim 93 wherein the step of epitaxially growing a monocrystalline oxide layer comprises growing a monocrystalline oxide layer having a thickness of about 5 - 6 nm.

95. The process of claim 93 wherein the step of thermally annealing comprises rapid thermal annealing.

96. The process of claim 93 wherein the step of thermally annealing comprises thermal annealing at a temperature between about 700° C and about 1000° C.

97. The process of claim 90 wherein the step of thermally annealing comprises rapid thermal annealing.

98. The process of claim 90 wherein the step of thermally annealing comprises annealing at a temperature between about 700° C and about 1000° C.

99. The process of claim 90 wherein the step of thermally annealing comprises the step of laser annealing.

100. The process of claim 90 wherein the step of providing a monocrystalline oxide layer comprises providing an oxide layer comprising Sr_xBa_!._xTiO₃ where x ranges from O to l.

101. The process of claim 100 wherein the step of forming a template layer comprises capping the monocrystalline oxide layer with 1-10 monolayers of a material selected from titanium, titanium and oxygen, strontium, and strontium and oxygen.

102. The process of claim 101 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises epitaxially depositing a layer selected from GaAs, AlGaAs, GaAsP, and GalnP.

103. The process of claim 102 wherein the step of thermally annealing comprises the step of rapid thermal annealing to a temperature between about 700° C and about 1000° C.

104. The process of claim 101 further comprises the step of depositing a buffer layer overlying the template layer.

105. The process of claim 104 wherein the step of depositing a buffer layer comprises epitaxially depositing a superlattice layer of a material selected from GaAs_xP _x where x ranges from 0 to 1 and Iri_yGa ,._y P where y ranges from 0 to 1.

106. The process of claim 105 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises epitaxially depositing a layer selected from GaAs, AlGaAs, GaAsP, GalnAs, InP and GalnP.

107. The process of claim 101 wherein the step of forming a template layer comprises capping the monocrystalline oxide layer with 1-10 monolayers of a material selected from Ge-Sr and Ge-Ti.

108. The process of claim 107 further comprising the step of epitaxially depositing a buffer layer of germanium.

109. The process o claim 101 wherein the step of forming a template layer comprises the steps of:

capping the monocrystalline oxide layer with 1-10 monolayers of ZnO; and

depositing 1-3 monolayers of zinc rich ZnO overlying the monolayers of ZnO.

110. The process of claim 109 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises epitaxially growing a layer selected from ZnSe and ZnSeS.

111. The process of claim 101 wherein the step of forming a template layer comprises the step of capping the monocrystalline oxide layer with 1-2 monolayers of SrS.

112. The process of claim 111 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises epitaxially growing a layer ofZnSeS.

113. The process of claim 90 wherein the step of providing a monocrystalline oxide layer comprises providing a monocrystalline oxide layer comprising a material selected from the group consisting of alkaline-earth-metal zirconates, and alkaline-earth-metal hafnates.

114. The process of claim 113 wherein the process of forming a template layer comprises capping the monocrystalline oxide layer with about 1-10 monolayers of a material M-N or M-O-N wherein M is selected from the group consisting of Zr, Hf, Sr, and Ba and N is selected from the group consisting of As, P, Ga, Al, and In.

115. The process of claim 114 wherein the step of epitaxially growing a monocrystalline compound semiconductor layer comprises epitaxially growing a layer comprising a material selected from InP and InGaAs.

116. The process of claim 115 further comprising forming a buffer layer comprising a superlattice comprising InGaAs overlying the template.

117. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline semiconductor substrate;

forming an accommodating buffer layer overlying the monocrystalline semiconductor substrate;

forming an amorphous intermediate layer between the monocrystalline semiconductor substrate and the accommodating buffer layer; and

epitaxially growing a monocrystalline compound semiconductor layer overlying the accommodating buffer layer.

118. The process of claim 117 wherein the step of forming an amorphous intermediate layer comprises the step of diffusing oxygen through the accommodating buffer layer to oxidize the monocrystalline semiconductor substrate.

119. The process of claim 117 wherein the step of forming an accommodating buffer layer comprises the steps of: growing an epitaxial buffer layer by a process selected from MBE, MOCVD, MEE, and ALE; and

after the step of epitaxially growing a monocrystalline compound semiconductor layer, thermally annealing the epitaxial buffer layer to convert the epitaxial layer to an amorphous layer.

120. The process of claim 117 wherein the step of providing a monocrystalline semiconductor substrate comprises providing a monocrystalline silicon substrate having a silicon oxide layer on a surface thereof.

121. The process of claim 120 wherein the step of forming an accommodating buffer layer comprises the steps of:

reacting a material selected from Sr_mBa,._m where m ranges from 0 to 1 and Sr_nBa„.jO where n ranges from 0 to 1 with the silicon oxide layer to form a template on the silicon substrate surface;

epitaxially depositing a monocrystalline layer comprising Sr_xBa_!__xTiO₃ where x ranges from 0 to 1 on the template; and

after the step of epitaxially growing a monocrystalline compound semiconductor layer, thermally annealing the monocrystalline layer comprising Sr_xBa,._xTiO₃ to convert the layer to an amorphous layer.

122. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline silicon substrate comprising a first region and a second region, the second region having an oxidized surface;

forming a CMOS circuit in the first region;

depositing a material comprising strontium onto the second region having an oxidized surface and reacting the material with the oxidized surface to form a first template layer;

depositing a monocrystalline oxide layer comprising strontium, titanium and oxygen overlying the first template layer by introducing strontium, titanium, and a partial pressure of oxygen to the template layer;

increasing the partial pressure of oxygen to grow an amorphous layer of silicon oxide on the second region;

terminating the step of depositing a monocrystalline oxide layer by depositing a second template layer comprising a monolayer comprising titanium;

depositing a layer of a monocrystalline compound semiconductor material comprising gallium and arsenic overlying the second template layer;

thermally annealing the monocrystalline oxide layer to convert the monocrystalline layer to an amorphous layer;

forming a semiconductor component in the layer of a monocrystalline compound semiconductor material; and

depositing a metallic conductor configured to electrically couple the CMOS circuit and the semiconductor component.

123. The process of claim 122 wherein the step of thermally annealing comprises the step of rapid thermal annealing at a temperature between about 700° C and about 1000° C.

124. The process of claim 122 wherein the step of thermally annealing comprises the step of thermally annealing at a temperature between about 700° C and about 1000° C in the presence of an over pressure of arsenic.

125. The process of claim 122 wherein the step of depositing a monocrystalline oxide layer comprises the step of depositing a monocrystalline oxide layer having a thickness of between 2 and 10 nm.

126. The process of claim 125 wherein the step of depositing a monocrystalline oxide layer comprises the step of depositing a monocrystalline oxide layer having a thickness of between 5 and 6 nm.

127. A communicating device including a monolithic integrated circuit, wherein the integrated circuit comprises: a monocrystalline Group IV semiconductor portion; an amorphous metal oxide layer overlying the monocrystalline Group IV semiconductor portion; a monocrystalline compound semiconductor portion overlying the amorphous metal oxide layer, wherein the monocrystalline compound semiconductor portion includes a feature selected from a group consisting of an amplifier, a signal modulator, a signal demodulator, a light emitting device, a light detecting device and an electromagnetic radiation emitter; and a digital logic portion formed in the monocrystalline Group IV semiconductor portion and coupled to the feature.

128. The communicating device of claim 127 wherein the amorphous metal oxide layer is formed by depositing a monocrystalline metal oxide layer and subsequently thermally annealing to convert the monocrystalline metal oxide to amorphous metal oxide.

129. The communicating device of claim 128 wherein the monocrystalline metal oxide layer has a crystalline orientation rotated by approximately 45° with respect to a crystalline orientation of the monocrystalline compound semiconductor portion.

130. The communicating device of claim 128 wherein the monocrystalline metal oxide layer has a crystalline orientation rotated by approximately 45° with respect to a crystalline orientation of the monocrystalline Group IV portion.

131. An integrated circuit comprising: an amorphous metal oxide layer; a monocrystalline compound semiconductor layer that overlies the amorphous metal oxide layer; and active devices, wherein all of the active devices within the integrated circuit lie at least partially within the monocrystalline compound semiconductor layer.

132. The integrated circuit of claim 131 further comprising a monocrystalline substrate underlying the amorphous metal oxide layer.

133. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline semiconductor substrate;

134. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline oxide layer having a surface;

135. A process for fabricating a semiconductor structure comprising the steps of:

providing a monocrystalline silicon substrate comprising a first region and a second region;

forming a CMOS circuit in the first region;

depositing a monocrystalline oxide layer overlying the second region;

terminating the step of depositing a monocrystalline oxide layer by depositing a template layer on the monocrystalline oxide layer;

depositing a layer of a monocrystalline compound semiconductor material overlying the template layer;

136. A process for fabricating a semiconductor structure comprising the steps of:

selecting a monocrystalline semiconductor substrate having a first lattice constant;

selecting a material that when properly oriented has a second lattice constant and crystalline structure such that the material can be deposited as a monocrystalline film overlying the monocrystalline semiconductor substrate, the second lattice constant different than the first lattice constant;

depositing a monocrystalline film of the material overlying the monocrystalline semiconductor substrate, the monocrystalline film being strained because the first lattice constant is different than the second lattice constant;

forming an amorphous interface layer at an interface between the monocrystalline film and the monocrystalline semiconductor substrate, the amorphous interface layer having a thickness sufficient to relieve the strain in the monocrystalline film;

selecting a compound semiconductor material having a third lattice constant that is different than the second lattice constant and that when properly oriented can be deposited on the monocrystalline film as a monocrystalline compound semiconductor layer;

epitaxially depositing a monocrystalline layer of the compound semiconductor material overlying the monocrystalline film, the monocrystalline layer characterized by a third lattice constant and being strained because the third lattice constant is different than the second lattice constant; and

annealing the monocrystalline film to convert the monocrystalline film to an amorphous film to relieve the strain in the monocrystalline layer of compound semiconductor material.

137. The process of claim 136 wherein the third lattice constant is different than the first lattice constant.

138. The process of claim 136 further comprising the step of forming a first template layer overlying the monocrystalline substrate to nucleate the step of depositing a monocrystalline film.

139. The process of claim 138 further comprising the step of forming a second template layer overlying the monocrystalline film to nucleate the step of epitaxially depositing a monocrystalline layer.