JP5093905B2 - 半導体装置および半導体装置を製造する方法 - Google Patents
半導体装置および半導体装置を製造する方法 Download PDFInfo
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Description
(実施形態1)
まず、本発明の実施形態1における半導体装置を、図5を用いて説明する。
以下に、実施形態2における半導体装置を製造する方法を、図7および図8A〜図8Gを用いて説明する。
以下に、実施形態3における半導体装置を製造する方法を説明する。
以下に、本発明における半導体装置の基板として、SOI(Silicon On Insrator)基板が用いられる場合の一例について図18を用いて説明する。
上述した実施形態1〜実施形態5では、ゲート電極とそれに隣接するゲート電極との間隔と、サイドウォールの幅dとの関係について、特に規定していない。以下に、ゲート電極とそれに隣接するゲート電極の間隔が、サイドウォールの幅dの2倍より短い半導体装置である実施形態6を、図19A、図19B、図20および図21を用いて説明する。
202 活性領域
203 ゲート酸化膜
204 ゲート電極
205 ゲート電極側壁絶縁膜
206 ソース・ドレイン領域
207 コンタクト孔
Claims (19)
- 素子分離領域と活性領域を有し、該活性領域上にゲート酸化膜を介してゲート電極が形成され、該ゲート電極の両側にソース領域およびドレイン領域が形成されている半導体装置であって、
該活性領域と該ゲート酸化膜が接する第1の面より上に、該ソース領域およびドレイン領域の一部が、該ゲート電極の側部に形成されたゲート電極側壁絶縁膜を介して存在し、
該ソース領域および該ドレイン領域の少なくとも一方と、該ソース領域および該ドレイン領域の該少なくとも一方に電気的に接続される配線とが接する第2の面が、該第1の面に対して傾いており、
該ゲート電極から該素子分離領域までの距離aは、該ゲート電極側壁絶縁膜の厚みbと、該素子分離領域に対して該ゲート電極を位置合わせするときの位置合わせマージンcとに対して、関係式a>b+cを満たすよう設定され、かつ、該ゲート電極側壁絶縁膜と、該ソース領域および該ドレイン領域の該少なくとも一方の、該第1の面より上に位置する部分とを合わせたゲート側壁部のゲート長方向の幅dは、該ゲート電極から該素子分離領域までの距離aと、該位置合わせマージンcとに対して、関係式d>a+cを満たすよう設定されており、該位置合わせマージンcは、該ゲート電極長の三分の一である半導体装置。 - 前記第2の面が凹凸を有している請求項1に記載の半導体装置。
- 前記ソース領域および前記ドレイン領域の前記少なくとも一方のある部分が、前記素子分離領域の一部を覆っている請求項1に記載の半導体装置。
- 前記第1の面に対する垂直方向における、前記ソース領域および前記ドレイン領域の前記少なくとも一方の該第1の面からの高さが、前記ゲート電極に近いほど高い、請求項1〜3のうちの1つに記載の半導体装置。
- 前記第2の面が曲線形状である請求項1に記載の半導体装置。
- 前記ソース領域および前記ドレイン領域の前記少なくとも一方の表面と、配線を接続するためのコンタクト孔の一部が、該ソース領域および該ドレイン領域の該少なくとも一方の表面に位置する請求項1に記載の半導体装置。
- 前記ゲート電極長手方向に対する垂直方向であって、該コンタクト孔の中心を通る垂直断面に関し、該垂直断面における該ゲート電極から離れた方に位置する該コンタクト孔の端から該ゲート電極までの距離が、該ゲート電極の端から、活性領域と素子分離領域の境界までの距離よりも長い、請求項6に記載の半導体装置。
- 前記ゲート電極長手方向に対する垂直方向であって、該コンタクト孔の中心を通る垂直断面に関し、該垂直断面における該コンタクト孔の開口部の幅は、該ゲート電極の端から、前記活性領域と前記素子分離領域の境界までの距離よりも長い、請求項1に記載の半導体装置。
- 前記ゲート電極長手方向に対する垂直方向に関して、前記ゲート電極の端から前記活性領域と前記素子分離領域の境界までの距離は、該ゲート電極の幅(前記半導体装置のゲート長)よりも短い、請求項6に記載の半導体装置。
- 前記ソース領域および前記ドレイン領域を構成する積み上げ層中の不純物の拡散係数が、前記半導体基板中の不純物の拡散係数よりも大きい、請求項1〜9のうちの1つに記載の半導体装置。
- 前記積み上げ層中の不純物の拡散係数が、前記半導体基板中の不純物の拡散係数の2倍から100倍である請求項10に記載の半導体装置。
- 前記積み上げ層が多結晶シリコンである請求項10または11に記載の半導体装置。
- 前記多結晶シリコンが、柱状結晶である請求項12に記載の半導体装置。
- 前記多結晶シリコンのグレインサイズは、50nm以下である請求項12に記載の半導体装置。
- 前記ゲート電極、前記ソース領域、および前記ドレイン領域の表面が、該ゲート電極、該ソース領域、および該ドレイン領域を構成する多結晶シリコン膜の上に形成された高融点金属シリサイド膜により覆われている請求項1に記載の半導体装置。
- 前記第1の面から、前記ソース領域および前記ドレイン領域と前記活性領域の接合面までの深さが、前記ゲート電極側壁絶縁膜の幅に対して0.8倍〜2倍である請求項1に記載の半導体装置。
- 請求項1に記載の半導体装置を製造する方法であって、
シリコンエッチングに対して耐性のある材料でシリコン基板上に素子分離領域を形成する工程と、
ゲート絶縁膜、ゲート電極、ゲート側壁絶縁膜を順次形成する工程と、
活性領域に対して1つのゲート電極が存在する場合、ゲート電極長手方向に対する垂直方向であるゲート長方向における該ゲート電極から該素子分離領域までの幅の値よりも厚い膜厚の多結晶シリコン膜を被着する工程と、
該ゲート電極上部の該多結晶シリコン膜がなくなるまで異方性エッチングを行い、該被着された多結晶シリコン膜のうち、該ゲート電極の両側に該ゲート側壁絶縁膜を介して位置するソース領域およびドレイン領域となる部分を残す工程と、
を包含する半導体装置を製造する方法。 - ドナーまたはアクセプタとなる不純物を、前記残された部分に導入することにより、ソース領域およびドレイン領域を形成するイオン注入工程をさらに有し、
前記ゲート電極がドナーまたはアクセプタとなる不純物が導入されることにより形成され、
該ソース領域、該ドレイン領域および該ゲート電極に、該ドナーまたは該アクセプタとなる不純物の導入は、イオン注入により同時に行われる請求項17に記載の半導体装置を製造する方法。 - 請求項1に記載の半導体装置を製造する方法であって、
シリコンエッチングに対して耐性のある材料でシリコン基板上に素子分離領域を形成する工程と、
ゲート絶縁膜、ゲート電極、ゲート側壁絶縁膜を順次形成する工程と、
多結晶シリコン膜を被着する工程と、
ゲート電極上部の該多結晶シリコン膜がなくなるまで異方性エッチングを行う工程と、
該ゲート電極側壁に、ゲート側壁絶縁膜を介して形成された多結晶シリコン膜の一部を、該多結晶シリコン膜が分離されて、該ゲート電極の両側に該ゲート側壁絶縁膜を介して位置する前記ソース領域および前記ドレイン領域となるように除去する工程と、
を包含する半導体装置を製造する方法。
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