JP5085829B2 - 集積回路チップ構造 - Google Patents

集積回路チップ構造 Download PDF

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Publication number
JP5085829B2
JP5085829B2 JP2002131172A JP2002131172A JP5085829B2 JP 5085829 B2 JP5085829 B2 JP 5085829B2 JP 2002131172 A JP2002131172 A JP 2002131172A JP 2002131172 A JP2002131172 A JP 2002131172A JP 5085829 B2 JP5085829 B2 JP 5085829B2
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JP
Japan
Prior art keywords
integrated circuit
pad
chip
mode
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002131172A
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English (en)
Japanese (ja)
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JP2003332440A5 (https=
JP2003332440A (ja
Inventor
ムウ−シュン・リン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Megica Corp
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Priority to JP2002131172A priority Critical patent/JP5085829B2/ja
Publication of JP2003332440A publication Critical patent/JP2003332440A/ja
Publication of JP2003332440A5 publication Critical patent/JP2003332440A5/ja
Application granted granted Critical
Publication of JP5085829B2 publication Critical patent/JP5085829B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
JP2002131172A 2002-05-07 2002-05-07 集積回路チップ構造 Expired - Fee Related JP5085829B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002131172A JP5085829B2 (ja) 2002-05-07 2002-05-07 集積回路チップ構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002131172A JP5085829B2 (ja) 2002-05-07 2002-05-07 集積回路チップ構造

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010097554A Division JP2010239137A (ja) 2010-04-21 2010-04-21 高性能サブシステムの設計および組立体

Publications (3)

Publication Number Publication Date
JP2003332440A JP2003332440A (ja) 2003-11-21
JP2003332440A5 JP2003332440A5 (https=) 2005-09-29
JP5085829B2 true JP5085829B2 (ja) 2012-11-28

Family

ID=29695855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002131172A Expired - Fee Related JP5085829B2 (ja) 2002-05-07 2002-05-07 集積回路チップ構造

Country Status (1)

Country Link
JP (1) JP5085829B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4640655B2 (ja) 2004-06-10 2011-03-02 日本電気株式会社 情報端末、ネットワーク接続設定プログラム、ネットワークシステムおよび方法
KR100630685B1 (ko) * 2004-06-22 2006-10-02 삼성전자주식회사 다른 칩을 경유하여 입력 신호를 전달하는 집적회로 장치및 집적회로 멀티 칩 패키지
JP2006080145A (ja) * 2004-09-07 2006-03-23 Nec Electronics Corp チップオンチップ型半導体集積回路装置
KR101049640B1 (ko) 2007-01-19 2011-07-14 램버스 인코포레이티드 반도체 장치
JP5801531B2 (ja) * 2009-10-16 2015-10-28 ルネサスエレクトロニクス株式会社 半導体パッケージ及びその製造方法
KR101190744B1 (ko) 2010-05-27 2012-10-12 에스케이하이닉스 주식회사 멀티칩 구조를 가지는 반도체 집적 회로
KR101211044B1 (ko) 2010-05-27 2012-12-12 에스케이하이닉스 주식회사 멀티칩 구조를 가지는 반도체 집적 회로
TWI483378B (zh) * 2013-01-04 2015-05-01 黃財煜 三維晶片堆疊結構
JP5908545B2 (ja) * 2014-08-14 2016-04-26 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 高性能サブシステムの設計および組立体

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58118123A (ja) * 1982-01-06 1983-07-14 Hitachi Ltd 半導体集積回路
JPS63126263A (ja) * 1986-11-17 1988-05-30 Hitachi Ltd 半導体集積回路装置
JP2531827B2 (ja) * 1990-04-25 1996-09-04 株式会社東芝 半導体装置及びその製造方法
EP0767492A3 (en) * 1995-10-02 1998-09-09 Altera Corporation Integrated circuit test system
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
JP2000022072A (ja) * 1998-07-07 2000-01-21 Matsushita Electric Ind Co Ltd マルチチップモジュール

Also Published As

Publication number Publication date
JP2003332440A (ja) 2003-11-21

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