JP5048420B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5048420B2
JP5048420B2 JP2007212949A JP2007212949A JP5048420B2 JP 5048420 B2 JP5048420 B2 JP 5048420B2 JP 2007212949 A JP2007212949 A JP 2007212949A JP 2007212949 A JP2007212949 A JP 2007212949A JP 5048420 B2 JP5048420 B2 JP 5048420B2
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Prior art keywords
internal connection
connection terminal
wiring pattern
metal layer
recess
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JP2007212949A
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English (en)
Japanese (ja)
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JP2009049134A (ja
JP2009049134A5 (enExample
Inventor
拓也 風間
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2007212949A priority Critical patent/JP5048420B2/ja
Priority to US12/190,789 priority patent/US7719123B2/en
Priority to KR1020080079244A priority patent/KR20090018576A/ko
Priority to EP08162325A priority patent/EP2026380A3/en
Priority to CNA2008101459885A priority patent/CN101369546A/zh
Publication of JP2009049134A publication Critical patent/JP2009049134A/ja
Priority to US12/749,758 priority patent/US8148254B2/en
Publication of JP2009049134A5 publication Critical patent/JP2009049134A5/ja
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Publication of JP5048420B2 publication Critical patent/JP5048420B2/ja
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007212949A 2007-08-17 2007-08-17 半導体装置及びその製造方法 Active JP5048420B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2007212949A JP5048420B2 (ja) 2007-08-17 2007-08-17 半導体装置及びその製造方法
KR1020080079244A KR20090018576A (ko) 2007-08-17 2008-08-13 반도체 장치의 제조 방법 및 반도체 장치
EP08162325A EP2026380A3 (en) 2007-08-17 2008-08-13 Method of manufacturing semiconductor device
US12/190,789 US7719123B2 (en) 2007-08-17 2008-08-13 Method of manufacturing semiconductor device
CNA2008101459885A CN101369546A (zh) 2007-08-17 2008-08-15 制造半导体器件的方法
US12/749,758 US8148254B2 (en) 2007-08-17 2010-03-30 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007212949A JP5048420B2 (ja) 2007-08-17 2007-08-17 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009049134A JP2009049134A (ja) 2009-03-05
JP2009049134A5 JP2009049134A5 (enExample) 2010-07-01
JP5048420B2 true JP5048420B2 (ja) 2012-10-17

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JP2007212949A Active JP5048420B2 (ja) 2007-08-17 2007-08-17 半導体装置及びその製造方法

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Country Link
US (2) US7719123B2 (enExample)
EP (1) EP2026380A3 (enExample)
JP (1) JP5048420B2 (enExample)
KR (1) KR20090018576A (enExample)
CN (1) CN101369546A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103300A (ja) * 2008-10-23 2010-05-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7956471B2 (en) * 2008-11-12 2011-06-07 Freescale Semiconductor, Inc. Mold and substrate for use with mold
JP5383460B2 (ja) * 2009-12-04 2014-01-08 新光電気工業株式会社 半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5412539A (en) * 1993-10-18 1995-05-02 Hughes Aircraft Company Multichip module with a mandrel-produced interconnecting decal
JP3502776B2 (ja) * 1998-11-26 2004-03-02 新光電気工業株式会社 バンプ付き金属箔及び回路基板及びこれを用いた半導体装置
JP4707283B2 (ja) * 2001-08-30 2011-06-22 イビデン株式会社 半導体チップ
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP3614828B2 (ja) 2002-04-05 2005-01-26 沖電気工業株式会社 チップサイズパッケージの製造方法
JP2004193497A (ja) * 2002-12-13 2004-07-08 Nec Electronics Corp チップサイズパッケージおよびその製造方法
JP2008108849A (ja) 2006-10-24 2008-05-08 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
JP2009049134A (ja) 2009-03-05
US20090045529A1 (en) 2009-02-19
US20100184257A1 (en) 2010-07-22
EP2026380A3 (en) 2009-11-18
KR20090018576A (ko) 2009-02-20
US8148254B2 (en) 2012-04-03
EP2026380A2 (en) 2009-02-18
US7719123B2 (en) 2010-05-18
CN101369546A (zh) 2009-02-18

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