JP5025462B2 - 切り欠きゲート電極を有する半導体素子の製造方法 - Google Patents

切り欠きゲート電極を有する半導体素子の製造方法 Download PDF

Info

Publication number
JP5025462B2
JP5025462B2 JP2007504945A JP2007504945A JP5025462B2 JP 5025462 B2 JP5025462 B2 JP 5025462B2 JP 2007504945 A JP2007504945 A JP 2007504945A JP 2007504945 A JP2007504945 A JP 2007504945A JP 5025462 B2 JP5025462 B2 JP 5025462B2
Authority
JP
Japan
Prior art keywords
conductive layer
insulating layer
layer
semiconductor device
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007504945A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007531268A (ja
JP2007531268A5 (https=
Inventor
ケイ． オーロースキー、マリウス
ディ． バーネット、ジェームズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007531268A publication Critical patent/JP2007531268A/ja
Publication of JP2007531268A5 publication Critical patent/JP2007531268A5/ja
Application granted granted Critical
Publication of JP5025462B2 publication Critical patent/JP5025462B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2007504945A 2004-03-26 2005-01-21 切り欠きゲート電極を有する半導体素子の製造方法 Expired - Fee Related JP5025462B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/811,461 US7105430B2 (en) 2004-03-26 2004-03-26 Method for forming a semiconductor device having a notched control electrode and structure thereof
US10/811,461 2004-03-26
PCT/US2005/002133 WO2005104225A2 (en) 2004-03-26 2005-01-21 Method for forming a semiconductor device having a notched control electrode and structure thereof

Publications (3)

Publication Number Publication Date
JP2007531268A JP2007531268A (ja) 2007-11-01
JP2007531268A5 JP2007531268A5 (https=) 2008-03-06
JP5025462B2 true JP5025462B2 (ja) 2012-09-12

Family

ID=34990536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007504945A Expired - Fee Related JP5025462B2 (ja) 2004-03-26 2005-01-21 切り欠きゲート電極を有する半導体素子の製造方法

Country Status (5)

Country Link
US (1) US7105430B2 (https=)
EP (1) EP1728274A4 (https=)
JP (1) JP5025462B2 (https=)
CN (1) CN100536094C (https=)
WO (1) WO2005104225A2 (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320629C (zh) * 2004-06-28 2007-06-06 中芯国际集成电路制造(上海)有限公司 集成电路器件形成隔离物后修复等离子体损伤的方法
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
US8053849B2 (en) * 2005-11-09 2011-11-08 Advanced Micro Devices, Inc. Replacement metal gate transistors with reduced gate oxide leakage
EP1906461B1 (de) * 2006-09-26 2020-03-18 OSRAM Opto Semiconductors GmbH Verfahren zur Herstellung eines optoelektronischen Bauelements und optoelektronisches Bauelement
KR101263648B1 (ko) * 2007-08-31 2013-05-21 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조 방법.
JP2010027638A (ja) * 2008-07-15 2010-02-04 Sumitomo Electric Ind Ltd 半導体装置の製造方法および半導体装置
WO2010023608A2 (en) * 2008-08-25 2010-03-04 Nxp B.V. Low cost mos transistor for rf applications
US9128699B2 (en) * 2008-12-22 2015-09-08 Intel Corporation Method and system for queuing transfers of multiple non-contiguous address ranges with a single command
DE102010042229B4 (de) * 2010-10-08 2012-10-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zum Steigern der Integrität eines Gatestapels mit großem ε durch Erzeugen einer gesteuerten Unterhöhlung auf der Grundlage einer Nasschemie und mit den Verfahren hergestellter Transistor
US9166004B2 (en) * 2010-12-23 2015-10-20 Intel Corporation Semiconductor device contacts
US8383469B2 (en) * 2011-01-07 2013-02-26 Eastman Kodak Company Producing transistor including reduced channel length
US8314022B1 (en) * 2011-05-20 2012-11-20 Intermolecular, Inc. Method for etching gate stack
DE112014000641T5 (de) * 2013-02-01 2015-11-05 Ps4 Luxco S.A.R.L. Halbleitervorrichtung und Verfahren zu dessen Herstellung
US9412602B2 (en) 2013-03-13 2016-08-09 Asm Ip Holding B.V. Deposition of smooth metal nitride films
US8841182B1 (en) 2013-03-14 2014-09-23 Asm Ip Holding B.V. Silane and borane treatments for titanium carbide films
US8846550B1 (en) 2013-03-14 2014-09-30 Asm Ip Holding B.V. Silane or borane treatment of metal thin films
US9394609B2 (en) 2014-02-13 2016-07-19 Asm Ip Holding B.V. Atomic layer deposition of aluminum fluoride thin films
US10643925B2 (en) 2014-04-17 2020-05-05 Asm Ip Holding B.V. Fluorine-containing conductive films
KR102216575B1 (ko) 2014-10-23 2021-02-18 에이에스엠 아이피 홀딩 비.브이. 티타늄 알루미늄 및 탄탈륨 알루미늄 박막들
US9941425B2 (en) 2015-10-16 2018-04-10 Asm Ip Holdings B.V. Photoactive devices and materials
US9786491B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
US9786492B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
KR102378021B1 (ko) 2016-05-06 2022-03-23 에이에스엠 아이피 홀딩 비.브이. SiOC 박막의 형성
US10186420B2 (en) 2016-11-29 2019-01-22 Asm Ip Holding B.V. Formation of silicon-containing thin films
US10847529B2 (en) 2017-04-13 2020-11-24 Asm Ip Holding B.V. Substrate processing method and device manufactured by the same
US10504901B2 (en) 2017-04-26 2019-12-10 Asm Ip Holding B.V. Substrate processing method and device manufactured using the same
KR102627238B1 (ko) 2017-05-05 2024-01-19 에이에스엠 아이피 홀딩 비.브이. 산소 함유 박막의 형성을 제어하기 위한 플라즈마 강화 증착 공정
KR20190065962A (ko) 2017-12-04 2019-06-12 에이에스엠 아이피 홀딩 비.브이. 유전체와 금속 표면 상에 SiOC의 균일한 증착
US12359315B2 (en) 2019-02-14 2025-07-15 Asm Ip Holding B.V. Deposition of oxides and nitrides
US12341005B2 (en) 2020-01-17 2025-06-24 Asm Ip Holding B.V. Formation of SiCN thin films
US12142479B2 (en) 2020-01-17 2024-11-12 Asm Ip Holding B.V. Formation of SiOCN thin films

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
JP3350246B2 (ja) * 1994-09-30 2002-11-25 株式会社東芝 半導体装置の製造方法
KR100207472B1 (ko) * 1996-06-07 1999-07-15 윤종용 티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체장치 및 그 제조 방법
US6225168B1 (en) * 1998-06-04 2001-05-01 Advanced Micro Devices, Inc. Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
CN1216427C (zh) 1998-12-07 2005-08-24 英特尔公司 带凹槽栅极的晶体管
US6639191B2 (en) * 1999-01-25 2003-10-28 Ibiden Co., Ltd. Hot plate unit
US6596598B1 (en) * 2000-02-23 2003-07-22 Advanced Micro Devices, Inc. T-shaped gate device and method for making
US6399469B1 (en) * 2000-07-10 2002-06-04 Advanced Micro Devices, Inc. Fabrication of a notched gate structure for a field effect transistor using a single patterning and etch process
JP4447128B2 (ja) * 2000-07-12 2010-04-07 富士通マイクロエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
US6403456B1 (en) * 2000-08-22 2002-06-11 Advanced Micro Devices, Inc. T or T/Y gate formation using trim etch processing
US6440830B1 (en) * 2000-08-30 2002-08-27 Advanced Micro Devices, Inc. Method of copper-polysilicon gate formation
US6645840B2 (en) * 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6646326B1 (en) 2000-11-15 2003-11-11 Advanced Micro Devices, Inc. Method and system for providing source/drain-gate spatial overlap engineering for low-power devices
US6891235B1 (en) * 2000-11-15 2005-05-10 International Business Machines Corporation FET with T-shaped gate
JP4628644B2 (ja) * 2001-10-04 2011-02-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US7199011B2 (en) * 2003-07-16 2007-04-03 Texas Instruments Incorporated Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon

Also Published As

Publication number Publication date
US20050215008A1 (en) 2005-09-29
US7105430B2 (en) 2006-09-12
CN100536094C (zh) 2009-09-02
JP2007531268A (ja) 2007-11-01
WO2005104225A2 (en) 2005-11-03
WO2005104225A3 (en) 2006-06-08
EP1728274A4 (en) 2008-11-05
CN101091239A (zh) 2007-12-19
EP1728274A2 (en) 2006-12-06

Similar Documents

Publication Publication Date Title
JP5025462B2 (ja) 切り欠きゲート電極を有する半導体素子の製造方法
KR102365321B1 (ko) 다중 게이트 디바이스들을 위한 게이트 패턴화 공정
KR101770476B1 (ko) 반도체 컴포넌트와 FinFET 디바이스의 제조 방법
US8173506B2 (en) Method of forming buried gate electrode utilizing formation of conformal gate oxide and gate electrode layers
US10038066B2 (en) Uniform vertical field effect transistor spacers
JP2007208260A (ja) 二重仕事関数金属ゲートスタックを備えるｃｍｏｓ半導体装置
TWI804632B (zh) 半導體元件及其製作方法
TW201541525A (zh) 鰭型場效電晶體元件及其製造方法
US10832956B2 (en) Method and structure for forming transistors with high aspect ratio gate without patterning collapse
US11817503B2 (en) Semiconductor device
TW201541640A (zh) 鰭型場效電晶體元件及其製造方法
CN114823868A (zh) 半导体器件及其形成方法
CN114792723A (zh) 半导体装置及其制造方法
CN110783330A (zh) 半导体装置
CN110957364A (zh) 半导体装置
CN119300455A (zh) 半导体器件及其形成方法
JP2009277961A (ja) Ｃｍｉｓトランジスタの製造方法
KR101140001B1 (ko) 노칭된 제어 전극을 구비한 반도체 디바이스를 형성하는방법 및 그에 의한 구조
JP2007287793A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080121

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111006

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111018

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120425

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120514

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120522

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120619

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150629

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5025462

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees