CN1216427C - 带凹槽栅极的晶体管 - Google Patents

带凹槽栅极的晶体管 Download PDF

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CN1216427C
CN1216427C CN998141593A CN99814159A CN1216427C CN 1216427 C CN1216427 C CN 1216427C CN 998141593 A CN998141593 A CN 998141593A CN 99814159 A CN99814159 A CN 99814159A CN 1216427 C CN1216427 C CN 1216427C
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C·楚
T·A·莱特森
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Abstract

利用蚀刻过程由导电材料单层来制作出一个具有T型横截面栅极的晶体管。经过两次蚀刻之后形成具有凹槽型面的侧壁。凹槽使源极区和漏极区能被注入进衬底，并且可以在不生成栅极额外叠加电容的情况下进行热处理。减少叠加电容能提高晶体管的操作性能包括驱动电流。

Description

带凹槽栅极的晶体管
本发明涉及集成电路晶体管，特别涉及金属氧化物半导体晶体管栅极。
用标准的互补金属氧化物半导体集成电路制作而成的集成电路晶体管如MOS(金属氧化物半导体)场效应晶体管(MOSFET)具有源极区、漏极区和栅极。每一个MOSFETs具有n型掺杂多晶硅栅极。源极区和漏极区注入到硅衬底中，在源极区和漏极区之间及栅电极之下形成沟道区。由于存在叠加电容，所以不希望源极区和漏极区之间具有栅叠加。也就是说，在源极区和漏极区之间存在栅极叠加时，在栅极区和源极区/漏极区之间就会有叠加电容。因此希望叠加减少到最小。
控制栅极区和源极区/漏极区之间的叠加量需要对源极/漏极注入区进行热处理来满足深度最小的要求来配合。用于控制源极和漏极之间注入空间的一种技术是利用附加在栅极侧壁上的垫片，附加步骤是需要制作这些垫片。
由于上述原因和以下本领域技术人员在阅读和理解本说明书后将很清楚的其他原因，在晶体管技术中，要求晶体管的叠加电容少，处理步骤简化。
本发明记载了以上提到的MOSFET的问题和其它的问题，通过阅读和学习以下的说明书将得到了解。
在一个实施例中，本发明提供了一个集成电路晶体管，它包括源极，漏极和栅极，其中栅极是由一个单层形成的并具有顶部区、底部区及第一和第二相反对置的垂直侧壁。第一和第二的垂直侧壁有一个阶梯状表面，使得顶部区域的第一和第二的垂直侧壁之间的第一横向间距大于底部区域的第一和第二的垂直侧壁之间的第二横向间距。
在另外一个实施例中，一个集成电路晶体管栅极包括一个由导电材料制成的单层。栅极具有一个顶部区，一个底部区及第一和第二相反对置的垂直侧壁。第一和第二的垂直侧壁有一个阶梯状表面，使得顶部区的第一和第二的垂直侧壁之间的第一横向间距大于底部区的第一和第二的相对垂直侧壁之间的第二横向间距。
在另一个实施例中，描述了一种集成电路晶体管的制作方法。该方法包括制作一导电材料层，对导电材料进行第一次蚀刻以确定栅极的第一和第二相反对置的垂直侧壁，对导电材料进行第二次蚀刻以在第一和第二相反对置的垂直侧壁上形成凹槽区。凹槽区位于第一和第二相反对置的垂直侧壁底部，以使栅极的横截面近似成为一个T型。
图1所示的是由直面栅极和氧化垫片形成的晶体管。
图2是由多层材料形成的T型栅极。
图3是一个集成电路晶体管的横剖面图。
图4(a)-(f)是图3中的晶体管的制作方法。
图5是晶体管相对于蚀刻面上的晶体管漏电流图。
以下关于本发明的详细说明需参照作为说明书一部分的、以图解及实施本发明的特定实施例方式给出的相关附图。在几个附图中，用相同的标号来描述基本相同的部件。还可以应用其它的实施例，在不背离本发明范围的情况下，结构、逻辑及电气方面都可以改变。在以下的说明书中，所用的术语薄膜(Wafer)和衬底包括具有形成本发明的集成电路(IC)的暴露面的所有结构。下述的详细说明不对本发明构成限制，本发明的范围仅由所附的权利要求书及其等效范围进行限定。
在此所描述的晶体管有一个带凹槽的栅极。凹槽形成在源极区和漏极区的上面以控制源极扩展区和漏极扩展区的起始注入位置。带有凹槽的多晶硅栅极能使其从栅多晶硅层的边缘延伸到栅氧化层结，此偏移量带来了足够的横向扩散距离从而能栅极下面不发生横向扩散的情况下进行退火操作。
为了更全面地理解带有凹槽的栅极，参照附图1，图1给出了由正面栅极102和氧化垫片104形成的晶体管100。首先在衬底上形成一个栅氧化层106，然后在栅氧化层上沉淀一个栅多晶硅层，再在栅多晶硅层上进行掩摸和蚀刻即可形成栅电极102。值得注意的是，栅多晶硅层的侧边108和110是直的。然后在栅多晶硅的上面制作一个氧化层。氧化层被成型和蚀刻形成垫片104，垫片附着在栅多晶硅的直边上。源极区112和漏极区114利用氧化垫片形成衬底从而在结区或掺杂质区之间形成横向扩散。然后进行退火操作以进一步垂直地扩散源极区/漏极区。退火操作也会导致栅多晶硅下掺杂剂的横向扩散，可以推测的是，对氧化垫片进行沉淀、掩摸和蚀刻将会导致在多晶硅边缘和衬底边缘之间的距离发生变化。扩展区的横向扩散也因此经常会导致栅极无法控制的重叠现象，这种重叠将会产生一个叠加电容而导致晶体管性能的降低。另外，不希望有形成氧化衬底的额外处理步骤。
在图2中描述了一个有互换栅极的晶体管。栅极的横截面近似成“T”型。也就是说，栅极的顶部比底部宽。晶体管栅极不是由单层导电材料形成的，而是需要沉淀、定型和蚀刻第二个多晶硅层116。虽然此晶体管提供了一个较大的互连导体，但是形成氧化垫片需要多个步骤，需要另外的栅多晶硅沉淀、定型和蚀刻来形成电极的顶部。
为了减少叠加电容，同时使处理步骤最少。在此描述了由单层导体材料形成的带凹槽的栅极。参照图3，给出并描述了所制作的集成电路晶体管200的横剖面图。晶体管包括一个带有凹槽204的栅极202。栅极通过一个栅氧化层208与衬底250分开。源极区和漏极区212形成衬底(例如通过离子注入法)。源极区和漏极区包括扩展区210。扩展区之间及栅极下面的区域称作为晶体管体或者沟道区。凹槽204能使扩展区从凹槽的垂直表面扩散可控距离，这对于本领域技术人员来说这是可以理解的。也就是说，凹槽的深度限定了在栅极的底部和源极区/漏极区之间不会产生水平叠加的退火过程期间所用的横向扩散距离。对于本领域技术人员来说是可以理解的，图3中所示的晶体管是不完整的，它还必须与源极区/漏极区和栅极进行电气连接。为了充分说明本发明的要点，没有给出本发明的其他特征。
栅极202由一单层形成，并且具有顶部区203，底部区205，第一垂直侧壁207和第二相反对置的垂直侧壁209。第一和第二的垂直侧壁有一个阶梯状表面，从而顶部区的第一和第二的垂直侧壁之间的第一横向间距Y大于底部区的第一和第二的垂直侧壁之间的第二横向间距X。在一个实施例中，距离Y比距离X大约大20纳米，可以知道，Y和X之间的差值在包括但不限于10-40纳米之间的一个较宽范围内变化。晶体管的横截面成T型，以插入源极区和漏极区。
参照图4(a)-4(f)，下面给出了带有凹槽栅极的晶体管的制作方法。图4(a)示出了半导体衬底250、栅氧化层208和材料层如掺杂多晶硅层252的横剖面。晶体管区的衬底与相邻的电路绝缘和根据晶体管的需要掺杂质是可以理解的，而且是已有技术。掺杂多晶硅层252被掩摸和大容量蚀刻以限定栅极254的垂直侧壁的上边缘，如图4(b)所示。一旦进入栅氧化层，便在栅极的底部进行有选择地蚀刻以形成凹槽204，如图4(c)所示。第二次蚀刻需要高度细致地进行选择，不能除去太多的栅氧化层208。这样才能不穿透栅氧化层。在栅氧化层拐角的多晶硅层处有选择性地进行蚀刻以消除钝化现象，从而横向蚀刻多晶硅栅极以形成凹槽204。在选择蚀刻过程中，横向蚀刻速度接近饱和以便能够统一控制横向蚀槽。这样凹槽的形成接近于自我控制。对大容量多晶硅进行选择蚀刻的过程中，因为蚀刻控制参数的变化，所以可以认为是一个单独的步骤。选择性蚀刻是一个低压力高功率的蚀刻，所持续时间大约等于大容量多晶硅蚀刻的持续时间，大约需要20-40秒的时间。
在一个实施例中，选择性的蚀刻使用的是商业上可买得到的日立M511等离子蚀刻机，生产中的工序是按照表1中的设置进行的。
参数 单位  穿透蚀刻  大容量蚀刻  完成第一次蚀刻  完成第二次蚀刻
TCR温度 ℃  5  5  5  5
EL高度 mm  80  80  80  80
压力 Pa  0.4  0.4  0.4  1.2
RF功率 W  60  25  20  25
UW功率 W  400  400  400  400
气体A，氯气 ccm  25  25  25  0
气体B，氧气 ccm  3  3  3  5
气体C，溴化氢 ccm  75  75  75  100
线圈1 A  14  14  14  14
线圈2 A  17  17  17  14
线圈3 A  3  3  3  3
时间 sec  5  EP  24  12
He Backside KPa  1  1  1  1
Cont Plasma Y/n  N  Y  Y  n
                               表1
第一次蚀刻过程或者穿透蚀刻过程除去表面上的氧化物。大容量蚀刻除去栅氧化层的多晶硅。当除去所有的多晶硅后，通过测量蚀刻容器中的化学气体来确定蚀刻的终点(EP)。蚀刻步骤1使多晶硅的侧面变平，同上面所限定的凹槽一起形成最终的形状。可选的蚀刻步骤2用来除去蚀刻步骤1之后多晶硅上的任何残留物。
参照图4(d)，形成多晶硅栅极凹槽的外形以后，进行浅注入操作以形成源极区和漏极区的扩展区。注入操作从栅极的底部被横向地隔开。也就是，栅极顶部通过限定横向边界来规定浅注入区的形状，以使注入区不会扩展到栅极的下边。因此注入区基本不会扩展到栅极以下及利用栅极的顶部区域203的侧壁表面限定的垂直平面257和258之外。
源极区和漏极区的扩展区必须垂直延伸进衬底最小的深度以减少电流扩散电阻。因此可对浅注入物进行热处理，或者进行退火处理，进一步扩散垂直注入区，图4(e)所示。退火操作也会使注入区横向扩散。通过控制退火操作，横向扩散距离能够被修整而与凹槽的深度相一致。这样，能够减少栅极和源极区/漏极区之间的叠加度。经过热处理之后，源极区和漏极区210在栅极的下边延伸到垂直平面257和258以外。然而源极区和漏极区210不能在栅极的下边延伸到由凹槽204的内表面限定的垂直平面以外。最后进行深层注入形成完整的源极区和漏极区。可以知道，进行深层注入将会提供一个低电阻触点。在晶体管元件和区域中掺杂质的技术是已有技术，在这里就不再进行进一步的说明。
制作带凹槽的晶体管栅极带来了许多好处。第一个好处是提供了定型的多晶硅层。随着晶体管尺寸的减小，处理层的成型变得比较困难。本发明的晶体管栅极能用栅极顶部的较大区域来定型多晶硅，而提供一个较小的栅氧化层接口表面。第二个好处是如上所述晶体管的叠加电容减少了。图5是晶体管电路性能相对于凹槽深度的曲线图。此图所示的是使用凹槽晶体管的环行振荡器的振荡频率的增长百分比，利用增加蚀刻时间而形成凹槽的深度，第一个采样点(a)没有包含凹槽，而其它采样点的凹槽深度不断增加，采样点(e)的槽口深度大约有15-20纳米，采样点(i)的凹槽深度大约有20-25纳米。当其他变量不变时，环行振荡器晶体管提高了晶体管减少的电容的性能。同时也可以看到，随着凹槽深度的增加，振荡器的性能也在提高，性能的提高有一个限度，随着凹槽深度的不断增加，晶体管的性能将有一个稳定或者下降的状态，于是，最后的一个采样点(j)的性能由于扩展区之间的阻抗未达到多晶硅栅极(负重叠)而开始下降。
本说明书公开了一种减少晶体管集成电路中叠加电容的方法，该方法包括利用蚀刻过程由材料单层形成具有T型截面晶体管栅极的步骤。在一个实施例中，进行两次蚀刻以形成带凹槽面的侧壁。这个凹槽允许插入源极区和漏极区并进行热处理，而不会产生额外的叠加电容。叠加电容的减少提高了晶体管的操作性能。
尽管给出了具体的实施例并对其进行了说明，但是本领域的普通技术人员可以用那些能达到同样目的结构来代替给出的具体实施例。本申请期望覆盖本发明的任何改进和变化方案，因此，本发明仅由权利要求书及同等范围的权利要求所限定。

Claims (9)

1.一种集成电路晶体管，它包括：
源极；
漏极；和
凹槽单层多晶硅栅极，该凹槽单层多晶硅栅极具有两个垂直侧壁，包括一个凹槽，其在所述栅极的每个垂直侧壁下面延伸的横向间距在5纳米和20纳米之间。
2.根据权利要求1所述的集成电路晶体管，其中所述凹槽单层多晶硅栅极具有一个底部区，所述源极延伸至该底部区。
3.根据权利要求2所述的集成电路晶体管，其中所述凹槽单层多晶硅栅极具有一个底部区，所述漏极延伸至该底部区。
4.根据权利要求1所述的集成电路晶体管，其中所述凹槽单层多晶硅栅极具有一个顶部区，所述源极延伸至正好在该底部区下方的区域。
5.根据权利要求4所述的集成电路晶体管，其中所述凹槽单层多晶硅栅极具有一个顶部区，所述漏极延伸至正好在该顶部区下方的区域。
6.一种集成电路晶体管栅极，其包括：
单层掺杂多晶硅，该集成电路晶体管栅极由单层掺杂多晶硅形成，具有顶部区、底部区和第一垂直侧壁、和与该第一垂直侧壁对置的第二垂直侧壁，
所述第一垂直侧壁和第二垂直侧壁有一个阶梯状表面，从而使顶部区第一和第二垂直侧壁之间的第一横向间距，比底部区第一和第二垂直侧壁之间的第二横向间距大10纳米至40纳米，从而在所述栅极的底部边缘处的底部区限定凹槽，所述凹槽从所述第一垂直侧壁在所述栅极下方向内延伸至第二垂直侧壁，所述源极和漏极没有显著地在所述栅极下方延伸超出第一、第二横向间距的差。
7.一种装置，其包括：
集成电路晶体管源极；
集成电路晶体管漏极；和
单层集成电路晶体管多晶硅栅极，该单层多晶硅栅极具有顶部区和底部区，该底部区比该顶部区窄，该底部区具有两个侧壁，每个侧壁具有凹槽，每个凹槽在所述栅极的下面延伸的横向间距在5纳米和20纳米之间，所述源极和漏极没有显著地在所述栅极下方延伸超出所述凹槽横向间距。
8.根据权利要求7所述的装置，其还包括在衬底上的栅极氧化层，包括集成电路晶体管。
9.根据权利要求7所述的装置，其对源极和漏极进行扩散热处理，使氧化层图案化和蚀刻以形成多个垫片。
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