JP5000609B2 - 結晶化方法 - Google Patents
結晶化方法 Download PDFInfo
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- JP5000609B2 JP5000609B2 JP2008227333A JP2008227333A JP5000609B2 JP 5000609 B2 JP5000609 B2 JP 5000609B2 JP 2008227333 A JP2008227333 A JP 2008227333A JP 2008227333 A JP2008227333 A JP 2008227333A JP 5000609 B2 JP5000609 B2 JP 5000609B2
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- 238000005530 etching Methods 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 14
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 12
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
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- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L27/1259—Multistep manufacturing methods
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- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
図7(A)〜(D)は、下層のシード領域を用いて制御された境界位置によって相対的に大きな結晶粒を形成するプロセスにおける各工程を示す。
以下、本発明の一実施例について具体的な数値を挙げて説明するが、本発明は、以下の説明にのみ限定されるものではない。
202 基板
204 シード領域
206 絶縁体層
208 開口部
210 活性半導体層
212 ソース
214 ドレイン
216 チャネル
218 ゲート誘電体
220 ゲート
222 結晶粒
224 平均結晶粒径
300 シード膜
302 上面
400 結晶粒
402 シード領域結晶粒径
402 平均粒径
402 粒径
404 直径
502 距離
600 ボトムゲート
700 第1の半導体膜
702 絶縁膜
704 開口部
706 第2の半導体膜
708 結晶粒界
800 半導体シード膜
802 基板
804 シード領域
808 ボトムゲート絶縁体層
809 開口部
810 活性半導体膜
812 トップゲート絶縁体層
814 トップゲート電極
Claims (12)
- 結晶粒を用いた活性半導体膜の位置制御された結晶化方法であって、
基板の上に、多結晶および単結晶からなる群より選ばれた結晶構造および結晶配向を有する第1の半導体膜を形成する工程と、
上記第1の半導体膜を選択的にエッチングして種結晶領域を形成する工程と、
上記種結晶領域の上に、非晶質構造を有する絶縁体層を積層する工程と、
上記絶縁体層に開口部を形成して上記種結晶領域を露出させる工程と、
上記絶縁体層の上に、第2の半導体膜を形成する工程と、
上記第2の半導体膜をレーザアニールする工程と、
上記レーザアニールに応じて上記第2の半導体膜を完全に溶融し、上記種結晶領域を部分的に溶融させる工程と、
上記種結晶領域と同じ結晶配向を有している第2の半導体膜中で結晶粒を上記種結晶領域から横成長させる工程と、
上記種結晶領域の上の第2の半導体膜を除去するために、上記結晶粒を上記第2の半導体膜中で横成長させた後の上記第2の半導体膜をエッチングする工程と、
残っている第2の半導体膜中にトランジスタ活性領域を形成する工程とを含み、
上記第1の半導体膜を選択的にエッチングする工程は、上記基板上に積層され、かつ、上記第1の半導体膜をエッチングして上記種結晶領域に隣接するボトムゲートを形成する工程を含み、
上記絶縁体層の形成工程は、上記絶縁体層を上記ボトムゲートおよび種結晶領域の上に形成することにより、ボトムゲート絶縁体層を形成する工程を含み、
上記トランジスタ活性領域を形成する工程は、上記ボトムゲートの上の第2の半導体膜中にトランジスタ活性領域を形成する工程を含んでいることを特徴とする結晶化方法。 - 結晶粒を用いた活性半導体膜の位置制御された結晶化方法であって、
基板の上に、多結晶および単結晶からなる群より選ばれた結晶構造および結晶配向を有する第1の半導体膜を形成する工程と、
上記第1の半導体膜を選択的にエッチングして種結晶領域を形成する工程と、
上記種結晶領域の上に、非晶質構造を有する絶縁体層を積層する工程と、
上記絶縁体層に開口部を形成して上記種結晶領域を露出させる工程と、
上記絶縁体層の上に、第2の半導体膜を形成する工程と、
上記第2の半導体膜をレーザアニールする工程と、
上記レーザアニールに応じて上記第2の半導体膜を完全に溶融し、上記種結晶領域を部分的に溶融させる工程と、
上記種結晶領域と同じ結晶配向を有している第2の半導体膜中で結晶粒を上記種結晶領域から横成長させる工程と、
上記種結晶領域の上の第2の半導体膜を除去するために、上記結晶粒を上記第2の半導体膜中で横成長させた後の上記第2の半導体膜をエッチングする工程と、
残っている第2の半導体膜中にトランジスタ活性領域を形成する工程とを含み、
上記種結晶領域を形成する工程は、結晶粒を有するように当該種結晶領域を形成する工程を含み、
上記絶縁体層に開口部を形成する工程では、上記開口部として、種結晶領域の前記結晶粒の平均粒径にほぼ等しい直径を有する開口部を形成することを特徴とする結晶化方法。 - 上記結晶配向を有する上記第1の半導体膜を形成する工程では、上記第1の半導体膜として、上面が(100)優先配向した第1の半導体膜を形成することを特徴とする請求項1または2記載の結晶化方法。
- 上記第2の半導体膜をレーザアニールする工程は、CO2レーザと連携してエキシマレーザによって、上記第2の半導体膜の上面を照射する工程を含んでいることを特徴とする請求項1〜3の何れか1項に記載の結晶化方法。
- 上記CO2レーザおよびエキシマレーザによる照射工程が、上記各レーザのビームの強度が、上記各レーザのビームが照射された領域中の各ポイントで均一になるようにフラッド照射する工程を含んでいることを特徴とする請求項4記載の結晶化方法。
- 上記種結晶領域と同じ結晶配向を有している上記第2の半導体膜中で結晶粒を上記種結晶領域から横成長させる工程は、10μm以上の横成長を伴って上記結晶粒を成長させる工程を含んでいることを特徴とする請求項1〜5の何れか1項に記載の結晶化方法。
- 選択的に上記第1の半導体膜をエッチングする工程は、2〜5μmの大きさの辺を有し、ダイヤモンド状および正方形状からなる群より選ばれる形状を有する種結晶領域を形成する工程を含んでいることを特徴とする請求項1〜6の何れか1項に記載の結晶化方法。
- 上記結晶粒を上記第2の半導体膜中で横成長させた後の上記第2の半導体膜をエッチングし、上記トランジスタ活性領域を形成する工程は、上記絶縁体層における開口部から2〜7μmの距離に、トランジスタチャネルを形成する工程を含んでいることを特徴とする請求項1〜7の何れか1項に記載の結晶化方法。
- さらに、上記トランジスタ活性領域に、ソース、ドレイン、およびチャネルを形成する工程を含んでいることを特徴とする請求項1〜8の何れか1項に記載の結晶化方法。
- さらに、上記トランジスタ活性領域の上にトップゲート誘電体を形成する工程と、上記トップゲート誘電体の上にトップゲートを形成する工程とを含んでいることを特徴とする請求項9記載の結晶化方法。
- 上記基板の上に第1の半導体膜を形成する工程は、ガラス、プラスチック、石英、石英ガラス、シリコン、およびシリコン・オン・インシュレータからなる群より選ばれる基板の上に上記第1の半導体膜を形成する工程を含んでいることを特徴とする請求項1〜10の何れか1項に記載の結晶化方法。
- 上記第1の半導体膜を形成する工程は、平均的な第1の粒径を有する結晶粒によって第1の半導体膜を形成する工程を含み、
上記第2の半導体膜中で結晶粒を横成長させる工程は、上記第1の粒径よりも大きな、平均的な第2の粒径を有する結晶粒を成長させる工程とを含んでいることを特徴とする請求項1〜11の何れか1項に記載の結晶化方法。
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US9087696B2 (en) | 2009-11-03 | 2015-07-21 | The Trustees Of Columbia University In The City Of New York | Systems and methods for non-periodic pulse partial melt film processing |
US9646831B2 (en) | 2009-11-03 | 2017-05-09 | The Trustees Of Columbia University In The City Of New York | Advanced excimer laser annealing for thin films |
US8440581B2 (en) | 2009-11-24 | 2013-05-14 | The Trustees Of Columbia University In The City Of New York | Systems and methods for non-periodic pulse sequential lateral solidification |
CN102770939B (zh) * | 2009-11-03 | 2015-12-02 | 纽约市哥伦比亚大学理事会 | 用于非周期性脉冲部分熔融膜处理的系统和方法 |
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US20130164436A1 (en) * | 2011-12-27 | 2013-06-27 | Ricoh Company | Thin film manufacturing apparatus, thin film manufacturing method, liquid droplet ejecting head, and inkjet recording apparatus |
KR20160063515A (ko) * | 2014-11-26 | 2016-06-07 | 삼성디스플레이 주식회사 | 트랜지스터, 이를 구비한 유기발광 표시장치, 및 유기발광 표시장치 제조방법 |
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