JP4998020B2 - 出力レベル安定化回路及びそれを用いたcml回路 - Google Patents
出力レベル安定化回路及びそれを用いたcml回路 Download PDFInfo
- Publication number
- JP4998020B2 JP4998020B2 JP2007056500A JP2007056500A JP4998020B2 JP 4998020 B2 JP4998020 B2 JP 4998020B2 JP 2007056500 A JP2007056500 A JP 2007056500A JP 2007056500 A JP2007056500 A JP 2007056500A JP 4998020 B2 JP4998020 B2 JP 4998020B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- cml
- output level
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
CML回路の出力レベル安定化回路であって、
前記CML回路の差動対トランジスタの一方及び電流源トランジスタとそれぞれ同一特性のトランジスタにより形成されたレプリカ回路と、
このレプリカ回路の出力と基準電圧とを比較してこの比較結果を前記レプリカ回路の電流源トランジスタの制御電圧として供給する比較回路と、
前記レプリカ回路の出力と前記比較回路の入力との間に設けられた可変インピーダンス回路と、
前記比較結果におけるノイズを検出するノイズ検出手段と、
このノイズ検出に応答して前記可変インピーダンス回路のインピーダンスを可変制御する制御手段と、を含み、
前記比較回路の比較結果を前記CML回路の電流源トランジスタの制御入力へ供給することにより、前記CML回路の出力レベルの安定化をなすようにしたことを特徴とする。
2 基準電圧発生回路
3 ノイズ検出部
4 カウンタ
T1,T2 CML回路の差動対トランジスタ
T3 CML回路の電流源トランジスタ
T4 レプリカ回路の電流源トランジスタ
T5 レプリカ回路の差動対トランジスタの一方
T61〜T6n スイッチング用トランジスタ
R1,R2 CML回路のドレイン負荷抵抗
R3 レプリカ回路のドレイン負荷抵抗
R4,R41〜R4n 帰還抵抗
R5,R6 テブナン抵抗
Claims (4)
- CML回路の出力レベル安定化回路であって、
前記CML回路の差動対トランジスタの一方及び電流源トランジスタとそれぞれ同一特性のトランジスタにより形成されたレプリカ回路と、
このレプリカ回路の出力と基準電圧とを比較してこの比較結果を前記レプリカ回路の電流源トランジスタの制御電圧として供給する比較回路と、
前記レプリカ回路の出力と前記比較回路の入力との間に設けられた可変インピーダンス回路と、
前記比較結果におけるノイズを検出するノイズ検出手段と、
このノイズ検出に応答して前記可変インピーダンス回路のインピーダンスを可変制御する制御手段と、を含み、
前記比較回路の比較結果を前記CML回路の電流源トランジスタの制御入力へ供給することにより、前記CML回路の出力の安定化をなすようにしたことを特徴とする出力レベル安定化回路。 - 前記可変インピーダンス回路は、複数の抵抗素子とこれら抵抗素子の各々に直列接続されたスイッチ素子との並列接続構成であり、前記制御手段により前記スイッチ素子のオンオフ制御をなすことを特徴とする請求項1記載の出力レベル安定化回路。
- 前記制御手段は、前記ノイズ検出手段に応答して増減制御されるカウンタであり、このカウンタの出力により前記スイッチ素子のオンオフ制御をなすことを特徴とする請求項2記載の出力レベル安定化回路。
- 請求項1〜3いずれか記載の出力レベル安定化回路を含むことを特徴とするCML回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007056500A JP4998020B2 (ja) | 2007-03-07 | 2007-03-07 | 出力レベル安定化回路及びそれを用いたcml回路 |
US12/032,208 US7609084B2 (en) | 2007-03-07 | 2008-02-15 | Output level stabilization circuit and CML circuit using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007056500A JP4998020B2 (ja) | 2007-03-07 | 2007-03-07 | 出力レベル安定化回路及びそれを用いたcml回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008219678A JP2008219678A (ja) | 2008-09-18 |
JP4998020B2 true JP4998020B2 (ja) | 2012-08-15 |
Family
ID=39741012
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007056500A Expired - Fee Related JP4998020B2 (ja) | 2007-03-07 | 2007-03-07 | 出力レベル安定化回路及びそれを用いたcml回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7609084B2 (ja) |
JP (1) | JP4998020B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2611028A1 (en) | 2011-12-30 | 2013-07-03 | Dialog Semiconductor GmbH | Multi-stage fully differential amplifier with controlled common mode voltage |
US11281249B2 (en) * | 2019-09-23 | 2022-03-22 | International Business Machines Corporation | Voltage sensitive current circuit |
US11204635B2 (en) | 2019-09-23 | 2021-12-21 | International Business Machines Corporation | Droop detection using power supply sensitive delay |
US11152920B2 (en) | 2019-09-23 | 2021-10-19 | International Business Machines Corporation | Voltage starved passgate with IR drop |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62265534A (ja) * | 1986-05-13 | 1987-11-18 | Minolta Camera Co Ltd | 光電色彩計 |
US4734593A (en) * | 1986-10-29 | 1988-03-29 | Advanced Micro Devices, Inc. | CML bias generator |
JPH01162915A (ja) * | 1987-12-18 | 1989-06-27 | Fujitsu Ltd | 定電流装置 |
JPH0273827U (ja) | 1988-11-25 | 1990-06-06 | ||
JP2767885B2 (ja) * | 1989-05-19 | 1998-06-18 | ソニー株式会社 | 光ディスク装置 |
JPH0541657A (ja) * | 1991-08-07 | 1993-02-19 | Nec Corp | 半導体集積回路 |
JPH05252020A (ja) * | 1992-03-06 | 1993-09-28 | Fujitsu Ltd | Cmos駆動回路 |
JPH07307658A (ja) | 1994-05-11 | 1995-11-21 | Hitachi Ltd | 半導体回路 |
DE19644996A1 (de) * | 1996-10-30 | 1998-05-07 | Thomson Brandt Gmbh | Eingangssignalverstärker |
KR100558488B1 (ko) * | 2003-08-26 | 2006-03-07 | 삼성전자주식회사 | 데이터 구동회로 및 이를 이용한 반도체 장치 |
JP4238106B2 (ja) * | 2003-09-25 | 2009-03-11 | 株式会社日立製作所 | 論理回路 |
JP2005347785A (ja) * | 2004-05-31 | 2005-12-15 | Toyota Industries Corp | 信号生成回路 |
JP4578896B2 (ja) * | 2004-08-26 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | クロックバッファ回路 |
US7425847B2 (en) * | 2006-02-03 | 2008-09-16 | Micron Technology, Inc. | Input buffer with optimal biasing and method thereof |
-
2007
- 2007-03-07 JP JP2007056500A patent/JP4998020B2/ja not_active Expired - Fee Related
-
2008
- 2008-02-15 US US12/032,208 patent/US7609084B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20080218199A1 (en) | 2008-09-11 |
JP2008219678A (ja) | 2008-09-18 |
US7609084B2 (en) | 2009-10-27 |
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