JP4995156B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4995156B2 JP4995156B2 JP2008203638A JP2008203638A JP4995156B2 JP 4995156 B2 JP4995156 B2 JP 4995156B2 JP 2008203638 A JP2008203638 A JP 2008203638A JP 2008203638 A JP2008203638 A JP 2008203638A JP 4995156 B2 JP4995156 B2 JP 4995156B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- marking
- built
- relay substrate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
12 第1半導体チップ
14 第1樹脂部
16 接着剤
17 ランド電極
18 ボンディングワイヤ
20 第2中継基板
22 第2半導体チップ
24 第3樹脂部
26 接着剤
27 ランド電極
28 ボンディングワイヤ
30 内蔵半導体装置
32 接着剤
34 第2樹脂部
36 パッド電極
38 ボンディングワイヤ
40 凹部
42 半田ボール
44 貫通接続部
46 パッド電極
48 半田端子
50 第1捺印部
52 第2捺印部
54 第3捺印部
100 半導体装置
Claims (8)
- 第1中継基板の上面に搭載された第1半導体チップと、
前記第1中継基板の上面に設けられ、前記第1半導体チップを封止する第1樹脂部と、
前記第1樹脂部の上面に設けられ、前記第1中継基板に電気的に接続する内蔵半導体装置と、
前記第1中継基板の上面に設けられ、前記第1樹脂部と前記内蔵半導体装置とを封止する第2樹脂部と、
前記内蔵半導体装置に設けられ、前記内蔵半導体装置を識別するための情報を示す第1捺印部と、
前記第2樹脂部に設けられ、半導体装置及び前記第1半導体チップのいずれか一方を識別するための情報を示す第2捺印部と、を具備し、
前記第1捺印部と前記第2捺印部とは、前記第2樹脂部の上方からみて重ならないように配置されていることを特徴とする半導体装置。 - 前記第1樹脂部に設けられ、前記第1半導体チップを識別するための情報を示す第3捺印部を具備し、
前記第3捺印部は、前記第2樹脂部の上方から見て、前記第1捺印部と前記第2捺印部とに重ならないように配置されていることを特徴とする請求項1記載の半導体装置。 - 前記第1捺印部は、インク捺印により形成されていることを特徴とする請求項1または2記載の半導体装置。
- 前記第3捺印部は、インク捺印により形成されていることを特徴とする請求項2記載の半導体装置。
- 前記インク捺印は、金属粉末を含有するインクを用いていることを特徴とする請求項3または4記載の半導体装置。
- 前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、
前記内蔵半導体装置は、前記第3樹脂部が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第2半導体チップが搭載された面と反対側の前記第2中継基板の面に設けられていることを特徴とする請求項1から5のいずれか一項記載の半導体装置。 - 前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、
前記内蔵半導体装置は、前記第2中継基板が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第3樹脂部の上面に設けられていることを特徴とする請求項1から5のいずれか一項記載の半導体装置。 - 前記第1中継基板に凹部が設けられていて、前記第1半導体チップは、前記凹部に搭載されていることを特徴とする請求項1から7のいずれか一項記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008203638A JP4995156B2 (ja) | 2008-08-06 | 2008-08-06 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008203638A JP4995156B2 (ja) | 2008-08-06 | 2008-08-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010040880A JP2010040880A (ja) | 2010-02-18 |
JP4995156B2 true JP4995156B2 (ja) | 2012-08-08 |
Family
ID=42013086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008203638A Expired - Fee Related JP4995156B2 (ja) | 2008-08-06 | 2008-08-06 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4995156B2 (ja) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH118328A (ja) * | 1997-06-17 | 1999-01-12 | Hitachi Ltd | 半導体装置およびその製造方法並びにその識別方法 |
JP4191908B2 (ja) * | 2001-04-18 | 2008-12-03 | 株式会社東芝 | 積層型半導体装置 |
JP2005123246A (ja) * | 2003-10-14 | 2005-05-12 | Seiko Epson Corp | 電子部品、圧電発振器、内蔵電子部品の認識方法および圧電振動子の認識方法 |
JP2008042111A (ja) * | 2006-08-10 | 2008-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5074738B2 (ja) * | 2006-10-24 | 2012-11-14 | リンテック株式会社 | 複合型半導体装置用スペーサーシート、及び複合型半導体装置の製造方法 |
JP2008166438A (ja) * | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
JP2009152463A (ja) * | 2007-12-21 | 2009-07-09 | Toyota Motor Corp | 半導体装置、半導体装置の識別装置、及び半導体装置の製造装置 |
-
2008
- 2008-08-06 JP JP2008203638A patent/JP4995156B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010040880A (ja) | 2010-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5601751B2 (ja) | 半導体装置 | |
JP4871280B2 (ja) | 半導体装置およびその製造方法 | |
US7511371B2 (en) | Multiple die integrated circuit package | |
CN102867800B (zh) | 将功能芯片连接至封装件以形成层叠封装件 | |
JP5192825B2 (ja) | 半導体装置およびその製造方法、ならびに積層半導体装置の製造方法 | |
JP5341337B2 (ja) | 半導体装置及びその製造方法 | |
JP2008166439A (ja) | 半導体装置およびその製造方法 | |
US7332808B2 (en) | Semiconductor module and method of manufacturing the same | |
JP2007123595A (ja) | 半導体装置及びその実装構造 | |
US7956453B1 (en) | Semiconductor package with patterning layer and method of making same | |
CN101322231B (zh) | 高密度三维半导体晶片封装 | |
KR20130090143A (ko) | 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법 | |
KR20030029743A (ko) | 플랙서블한 이중 배선기판을 이용한 적층 패키지 | |
JP5921297B2 (ja) | 積層型半導体装置、プリント回路板及び積層型半導体装置の製造方法 | |
CN104241233A (zh) | 晶圆级半导体封装及其制造方法 | |
CN102412225A (zh) | Bga半导体封装及其制造方法 | |
US20120018879A1 (en) | Stack package and method for manufacturing the same | |
CN102398886B (zh) | 具微机电元件的封装结构及其制法 | |
JP4995156B2 (ja) | 半導体装置 | |
CN104769712B (zh) | 包括嵌入式控制器裸芯的半导体器件和其制造方法 | |
JP2006286920A (ja) | 電子部品内蔵用リードフレーム、電子部品内蔵リードフレーム、および、樹脂封止型電子部品内蔵半導体装置 | |
JP3939707B2 (ja) | 樹脂封止型半導体パッケージおよびその製造方法 | |
CN104716115A (zh) | 传感器封装及其制造方法 | |
JP2008182264A (ja) | 半導体装置、その製造方法およびその検査方法 | |
JP5068133B2 (ja) | 半導体チップ積層構造体及び半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100402 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100616 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110804 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111220 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120410 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120509 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150518 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4995156 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150518 Year of fee payment: 3 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D02 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150518 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |