JP4976977B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4976977B2
JP4976977B2 JP2007270259A JP2007270259A JP4976977B2 JP 4976977 B2 JP4976977 B2 JP 4976977B2 JP 2007270259 A JP2007270259 A JP 2007270259A JP 2007270259 A JP2007270259 A JP 2007270259A JP 4976977 B2 JP4976977 B2 JP 4976977B2
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Japan
Prior art keywords
film
processed
silicon
resist
bsg
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Expired - Fee Related
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JP2007270259A
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English (en)
Japanese (ja)
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JP2009099792A (ja
JP2009099792A5 (https=
Inventor
雅貴 成田
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007270259A priority Critical patent/JP4976977B2/ja
Priority to US12/251,791 priority patent/US7732338B2/en
Publication of JP2009099792A publication Critical patent/JP2009099792A/ja
Publication of JP2009099792A5 publication Critical patent/JP2009099792A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2007270259A 2007-10-17 2007-10-17 半導体装置の製造方法 Expired - Fee Related JP4976977B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007270259A JP4976977B2 (ja) 2007-10-17 2007-10-17 半導体装置の製造方法
US12/251,791 US7732338B2 (en) 2007-10-17 2008-10-15 Method of fabricating semiconductor device with reduced pitch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007270259A JP4976977B2 (ja) 2007-10-17 2007-10-17 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009099792A JP2009099792A (ja) 2009-05-07
JP2009099792A5 JP2009099792A5 (https=) 2010-04-08
JP4976977B2 true JP4976977B2 (ja) 2012-07-18

Family

ID=40563909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007270259A Expired - Fee Related JP4976977B2 (ja) 2007-10-17 2007-10-17 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7732338B2 (https=)
JP (1) JP4976977B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018052760A1 (en) * 2016-09-13 2018-03-22 Applied Materials, Inc. Borane mediated dehydrogenation process from silane and alkylsilane species for spacer and hardmask application

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KR100881513B1 (ko) * 2007-05-18 2009-02-05 주식회사 동부하이텍 반도체 미세패턴 형성 방법
US8420542B2 (en) * 2011-05-27 2013-04-16 International Business Machines Corporation Method of patterned image reversal
CN103999191B (zh) * 2011-12-15 2016-10-19 英特尔公司 用于单次曝光-自对准的双重、三重以及四重图案化的方法
CN103311092B (zh) * 2012-03-12 2015-08-05 中芯国际集成电路制造(上海)有限公司 沟槽的刻蚀方法
US9153440B2 (en) * 2012-03-23 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device
CN103779263B (zh) * 2012-10-18 2017-03-08 中芯国际集成电路制造(上海)有限公司 一种基于自对准双图案的半导体器件的制造方法
CN103794476B (zh) * 2012-10-30 2017-09-22 中芯国际集成电路制造(上海)有限公司 自对准三重图形的形成方法
US9070559B2 (en) 2013-07-25 2015-06-30 Kabushiki Kaisha Toshiba Pattern forming method and method of manufacturing semiconductor device
US9613806B2 (en) * 2013-09-04 2017-04-04 Sandisk Technologies Llc Triple patterning NAND flash memory
CN103928313B (zh) * 2014-04-22 2017-12-15 上海华力微电子有限公司 一种小尺寸图形的制作方法
CN103928314B (zh) * 2014-04-22 2017-06-06 上海华力微电子有限公司 一种底部无负载的自对准双层图形的制作方法
CN110690117B (zh) * 2018-07-05 2023-10-20 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
WO2021237403A1 (en) 2020-05-25 2021-12-02 Yangtze Memory Technologies Co., Ltd. Memory device and method for forming the same
WO2021237407A1 (en) * 2020-05-25 2021-12-02 Yangtze Memory Technologies Co., Ltd. Memory device and method for forming the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748237A (en) * 1980-09-05 1982-03-19 Nec Corp Manufacture of 2n doubling pattern
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR20030007904A (ko) * 2000-06-06 2003-01-23 이케이씨 테크놀로지, 인코포레이티드 전자 재료 제조 방법
US6429123B1 (en) * 2000-10-04 2002-08-06 Vanguard International Semiconductor Corporation Method of manufacturing buried metal lines having ultra fine features
JP2002280388A (ja) * 2001-03-15 2002-09-27 Toshiba Corp 半導体装置の製造方法
JP2002359308A (ja) * 2001-06-01 2002-12-13 Toshiba Corp 半導体記憶装置及びその製造方法
US6638441B2 (en) * 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
JP2006032648A (ja) * 2004-07-16 2006-02-02 Toshiba Corp パターン形成方法を含む半導体装置の製造方法
US7910288B2 (en) * 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
JP4619839B2 (ja) * 2005-03-16 2011-01-26 株式会社東芝 パターン形成方法
US7291560B2 (en) * 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7575992B2 (en) * 2005-09-14 2009-08-18 Hynix Semiconductor Inc. Method of forming micro patterns in semiconductor devices
KR100744683B1 (ko) * 2006-02-27 2007-08-01 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100790999B1 (ko) * 2006-10-17 2008-01-03 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법
KR100817088B1 (ko) * 2007-02-16 2008-03-26 삼성전자주식회사 다마신 공정을 이용한 반도체 소자의 미세 금속 배선 패턴형성 방법
KR100822592B1 (ko) * 2007-03-23 2008-04-16 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018052760A1 (en) * 2016-09-13 2018-03-22 Applied Materials, Inc. Borane mediated dehydrogenation process from silane and alkylsilane species for spacer and hardmask application
US10410872B2 (en) 2016-09-13 2019-09-10 Applied Materials, Inc. Borane mediated dehydrogenation process from silane and alkylsilane species for spacer and hardmask application

Also Published As

Publication number Publication date
JP2009099792A (ja) 2009-05-07
US20090104786A1 (en) 2009-04-23
US7732338B2 (en) 2010-06-08

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