JP4956466B2 - 段差が形成された伝導層を有する印刷回路基板 - Google Patents
段差が形成された伝導層を有する印刷回路基板 Download PDFInfo
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- JP4956466B2 JP4956466B2 JP2008053285A JP2008053285A JP4956466B2 JP 4956466 B2 JP4956466 B2 JP 4956466B2 JP 2008053285 A JP2008053285 A JP 2008053285A JP 2008053285 A JP2008053285 A JP 2008053285A JP 4956466 B2 JP4956466 B2 JP 4956466B2
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- conductive layer
- printed circuit
- circuit board
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- 230000008054 signal transmission Effects 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000013461 design Methods 0.000 description 8
- 238000004088 simulation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005094 computer simulation Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0236—Electromagnetic band-gap structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09681—Mesh conductors, e.g. as a ground plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
また、本発明の他の目的は、段差が形成された伝導層を電磁気バンドギャップ構造物として用いることにより、目標とする特定周波数帯域のノイズを簡単に遮蔽できる段差が形成された伝導層を有する印刷回路基板を提供することにある。
また、本発明のさらに他の目的は、印刷回路基板を小型化、薄型化、軽量化することができ、製造工程の簡素化、製造時間及び費用の節減が可能である、段差が形成された伝導層を有する印刷回路基板を提供することにある。
本発明のその他の目的は下記の説明を通して容易に理解できよう。
また、本発明は、段差が形成された伝導層を電磁気バンドギャップ構造物として用いることにより、目標とする特定の周波数帯域のノイズを簡単に遮蔽することができる。
320 第2伝導層
330 第3伝導層
320a 基準領域
320b 連結領域
340 第1誘電層
345 第2誘電層
Claims (8)
- 印刷回路基板において、
信号伝達層(signal transmission layer)として用いられる伝導層が、複数の基準領域と、隣接するある二つの前記基準領域の間を連結するための連結領域とに区分され、
前記基準領域は、格子状に形成され、
前記連結領域は、前記基準領域より低い段差を有するように形成され、前記伝達層の上部から見た時、前記隣接するある二つの基準領域の間を一側コーナーを通して連結し、
前記連結領域と前記基準領域との間のブリッジ連結構造は、前記印刷回路基板に位置したノイズ源とノイズ遮蔽先との間のノイズ伝達可能経路上に繰り返し配置されることを特徴とする段差が形成された伝導層を有する印刷回路基板。 - 前記伝導層が、電源層(power layer)または接地層(ground layer)として用いられることを特徴とする請求項1に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記連結領域の下面または上面が、前記基準領域の下面または上面と同一平面上に存在するか、または前記基準領域の下面及び上面と異なる平面上に存在することを特徴とする請求項1または請求項2に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記連結領域が、前記伝導層を側面から見た時、前記隣接するある二つの基準領域の間を直線状または凹曲線状に連結することを特徴とする請求項1から請求項3までの何れか1項に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記連結領域が、前記伝導層の上部から見た時、直線状、破線状、及び格子縞状のうちの何れか一つのパターンを有することを特徴とする請求項1から請求項4までの何れか1項に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記連結領域が、前記伝導層に複数存在し、前記複数の連結領域は方向性をもって順次層厚が薄くなるか厚くなるように設計されることを特徴とする請求項1から請求項5までの何れか1項に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記連結領域と前記基準領域との間のブリッジ連結構造は、前記伝導層内で交互に繰り返されることを特徴とする請求項1から請求項6までの何れか1項に記載の段差が形成された伝導層を有する印刷回路基板。
- 前記印刷回路基板にはデジタル回路及びアナログ回路が搭載され、前記ノイズ源及び前記ノイズ遮蔽先は、前記印刷回路基板において前記デジタル回路と前記アナログ回路が搭載される各々の位置のうちの何れか一つ及び他の一つに対応することを特徴とする請求項1から請求項7までの何れか1項に記載の段差が形成された伝導層を有する印刷回路基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2007-0097721 | 2007-09-28 | ||
KR1020070097721A KR100914440B1 (ko) | 2007-09-28 | 2007-09-28 | 단차가 형성된 전도층을 갖는 인쇄회로기판 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009088471A JP2009088471A (ja) | 2009-04-23 |
JP4956466B2 true JP4956466B2 (ja) | 2012-06-20 |
Family
ID=40506893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008053285A Expired - Fee Related JP4956466B2 (ja) | 2007-09-28 | 2008-03-04 | 段差が形成された伝導層を有する印刷回路基板 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20090084582A1 (ja) |
JP (1) | JP4956466B2 (ja) |
KR (1) | KR100914440B1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5018763B2 (ja) * | 2008-12-22 | 2012-09-05 | 富士ゼロックス株式会社 | 印刷配線基板 |
KR101007288B1 (ko) | 2009-07-29 | 2011-01-13 | 삼성전기주식회사 | 인쇄회로기판 및 전자제품 |
DE102012215703B4 (de) * | 2012-09-05 | 2014-07-17 | Osram Gmbh | Verkleidungsvorrichtung für eine Decke oder eine Wand eines Raums |
CN105306740B (zh) * | 2015-12-03 | 2018-03-27 | 广东欧珀移动通信有限公司 | 降噪方法及装置 |
WO2017199712A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社村田製作所 | セラミック電子部品 |
CN108834323A (zh) * | 2018-06-15 | 2018-11-16 | 深圳崇达多层线路板有限公司 | 一种精细阶梯线路的制作方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02153365A (ja) * | 1988-12-06 | 1990-06-13 | Dainippon Printing Co Ltd | 原版複製方法 |
US5131140A (en) * | 1991-02-26 | 1992-07-21 | Hewlett-Packard Company | Method for evaluating plane splits in printed circuit boards |
JPH0581324A (ja) * | 1991-09-19 | 1993-04-02 | Nec Software Kansai Ltd | 図面・部品検索処理方式 |
JPH10241465A (ja) * | 1997-02-20 | 1998-09-11 | Tokai Rubber Ind Ltd | 異方導電フィルムの製法およびそれによって得られた異方導電フィルム |
US6356245B2 (en) | 1999-04-01 | 2002-03-12 | Space Systems/Loral, Inc. | Microwave strip transmission lines, beamforming networks and antennas and methods for preparing the same |
US6822526B2 (en) * | 2002-12-30 | 2004-11-23 | Intel Corporation | Voltage plane with high impedance link |
JP2004297619A (ja) | 2003-03-27 | 2004-10-21 | Kyocera Corp | 弾性表面波装置 |
US7148425B2 (en) * | 2004-01-29 | 2006-12-12 | National Sun Yat-Sen University | Power plane system of high-speed digital circuit for suppressing ground bounce noise |
US7253788B2 (en) * | 2004-09-08 | 2007-08-07 | Georgia Tech Research Corp. | Mixed-signal systems with alternating impedance electromagnetic bandgap (AI-EBG) structures for noise suppression/isolation |
JP4671333B2 (ja) | 2005-03-18 | 2011-04-13 | 株式会社リコー | 多層プリント回路基板と電子機器 |
JP4676238B2 (ja) * | 2005-04-18 | 2011-04-27 | 株式会社日立製作所 | バックプレーンバス用メインボード、および、それを用いたルータシステム、ストレージシステム |
TW200818451A (en) * | 2006-06-02 | 2008-04-16 | Renesas Tech Corp | Semiconductor device |
-
2007
- 2007-09-28 KR KR1020070097721A patent/KR100914440B1/ko not_active IP Right Cessation
-
2008
- 2008-01-29 US US12/010,750 patent/US20090084582A1/en not_active Abandoned
- 2008-03-04 JP JP2008053285A patent/JP4956466B2/ja not_active Expired - Fee Related
-
2012
- 2012-02-03 US US13/365,755 patent/US20120138338A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR100914440B1 (ko) | 2009-08-28 |
KR20090032456A (ko) | 2009-04-01 |
US20090084582A1 (en) | 2009-04-02 |
JP2009088471A (ja) | 2009-04-23 |
US20120138338A1 (en) | 2012-06-07 |
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