JP4939756B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP4939756B2
JP4939756B2 JP2005018020A JP2005018020A JP4939756B2 JP 4939756 B2 JP4939756 B2 JP 4939756B2 JP 2005018020 A JP2005018020 A JP 2005018020A JP 2005018020 A JP2005018020 A JP 2005018020A JP 4939756 B2 JP4939756 B2 JP 4939756B2
Authority
JP
Japan
Prior art keywords
film
wiring pattern
pattern
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005018020A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005244203A (ja
JP2005244203A5 (enExample
Inventor
舜平 山崎
博信 小路
康行 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2005018020A priority Critical patent/JP4939756B2/ja
Publication of JP2005244203A publication Critical patent/JP2005244203A/ja
Publication of JP2005244203A5 publication Critical patent/JP2005244203A5/ja
Application granted granted Critical
Publication of JP4939756B2 publication Critical patent/JP4939756B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
JP2005018020A 2004-01-26 2005-01-26 半導体装置の作製方法 Expired - Fee Related JP4939756B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005018020A JP4939756B2 (ja) 2004-01-26 2005-01-26 半導体装置の作製方法

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2004017652 2004-01-26
JP2004017634 2004-01-26
JP2004017634 2004-01-26
JP2004017652 2004-01-26
JP2005018020A JP4939756B2 (ja) 2004-01-26 2005-01-26 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2005244203A JP2005244203A (ja) 2005-09-08
JP2005244203A5 JP2005244203A5 (enExample) 2008-01-24
JP4939756B2 true JP4939756B2 (ja) 2012-05-30

Family

ID=35025561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005018020A Expired - Fee Related JP4939756B2 (ja) 2004-01-26 2005-01-26 半導体装置の作製方法

Country Status (1)

Country Link
JP (1) JP4939756B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008209797A (ja) * 2007-02-27 2008-09-11 Sumitomo Heavy Ind Ltd レーザ照射装置、及び、露光方法
WO2011077978A1 (en) * 2009-12-25 2011-06-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device
JP5708191B2 (ja) 2010-05-19 2015-04-30 セントラル硝子株式会社 保護膜形成用薬液
WO2011155407A1 (ja) * 2010-06-07 2011-12-15 セントラル硝子株式会社 保護膜形成用薬液
US9228120B2 (en) 2010-06-07 2016-01-05 Central Glass Company, Limited Liquid chemical for forming protecting film
WO2012002243A1 (ja) * 2010-06-28 2012-01-05 セントラル硝子株式会社 撥水性保護膜形成剤、撥水性保護膜形成用薬液と該薬液を用いたウェハの洗浄方法
JP5712670B2 (ja) * 2011-02-25 2015-05-07 セントラル硝子株式会社 撥水性保護膜形成薬液
JP5716527B2 (ja) * 2010-06-28 2015-05-13 セントラル硝子株式会社 撥水性保護膜形成用薬液と該薬液を用いたウェハの洗浄方法
SG186761A1 (en) * 2010-06-28 2013-02-28 Central Glass Co Ltd Water repellent protective film forming agent, liquid chemical for forming water repellent protective film, and wafer cleaning method using liquid chemical
KR101396271B1 (ko) * 2010-06-30 2014-05-16 샌트랄 글래스 컴퍼니 리미티드 웨이퍼의 세정방법
JP2012033880A (ja) * 2010-06-30 2012-02-16 Central Glass Co Ltd 撥水性保護膜形成用薬液
WO2012002200A1 (ja) * 2010-06-30 2012-01-05 セントラル硝子株式会社 ウェハの洗浄方法
US9117764B2 (en) 2010-08-27 2015-08-25 Tokyo Electron Limited Etching method, substrate processing method, pattern forming method, method for manufacturing semiconductor element, and semiconductor element
WO2013080900A1 (en) * 2011-12-02 2013-06-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP6306278B2 (ja) * 2012-04-09 2018-04-04 Jsr株式会社 半導体素子、半導体基板、感放射線性樹脂組成物、保護膜および表示素子

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3926076B2 (ja) * 1999-12-24 2007-06-06 日本電気株式会社 薄膜パターン形成方法
JP2002313226A (ja) * 2001-04-12 2002-10-25 Fujitsu Ltd 薄型表示装置の電極形成方法および電極材料

Also Published As

Publication number Publication date
JP2005244203A (ja) 2005-09-08

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