JP4932701B2 - トレンチ型半導体デバイス及びその製造方法 - Google Patents
トレンチ型半導体デバイス及びその製造方法 Download PDFInfo
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Description
(a) 互いに反対側に位置した第1と第2の主表面を有し、高濃度ドープ領域よりも上方の第1の主表面のところに低濃度ドープ領域を有するシリコン半導体本体を用意するステップを有し、前記低濃度ドープ領域と前記高濃度ドープ領域の両方は、第1の導電型を呈するようドープされ、前記低濃度ドープ領域は、前記高濃度ドープ領域よりもドーピング度が低く、
(b) 前記第1の主表面上に開口部を備えたマスクを形成するステップを有し、
(c) 前記マスクの前記開口部を通ってトレンチを形成するステップを有し、前記トレンチは、前記第1の主表面から前記第2の主表面に向かって前記低濃度ドープ領域を通って前記高濃度ドープ領域の方へ延びており、
(d) 前記トレンチの側壁及び底部並びに前記第1の主表面にトレンチ絶縁層を被着させるステップを有し、
(e) 前記トレンチ絶縁層を前記第1の主表面に隣接して位置する前記トレンチの前記側壁の頂部から除去し、後に露出状態のシリコンが前記トレンチの前記側壁の前記頂部のところに残されるようにするステップを有し、
(f) シリコンを前記露出シリコン上で選択的に成長させてシリコンを前記トレンチの前記頂部のところで成長させ、前記トレンチの前記頂部に施栓するステップを有する方法であって、
該方法は、前記半導体デバイスの動作状態において前記低濃度ドープ領域を空乏化させて前記低濃度ドープ領域が前記動作状態における電圧に耐えることができるようにする構造体を形成するステップを更に有する方法が提供される。
(h) 第1の導電型のものであるようドープされた半導体のソース領域を前記第1の主表面のところ又はこれに隣接すると共に前記本体領域と接触して形成するステップと、
(i) 前記ソース領域と前記高濃度ドープ領域との間における前記本体領域中の導通状態を制御する絶縁ゲートを形成するステップとを更に有するとよい。
外側トレンチ絶縁層を前記トレンチの前記側壁及び頂面に被着させるステップと、
前記外側トレンチ絶縁層を前記トレンチの前記底部から除去するステップと、
半絶縁性ポリシリコン(SIPOS)を前記トレンチ内に成膜するステップと、
トレンチ絶縁層を被着させるステップとを更に有するのがよい。
シリコンを前記トレンチの前記頂部のところの露出状態にある前記側壁上で選択的に成長させて、互いに反対側の側壁上で成長したシリコン相互間に隙間が後に残るようにするサブステップと、
別のシリコン層を前記第1の主表面に被着させて前記トレンチの前記隙間に施栓するサブステップと、
前記第1の主表面に被着させた前記シリコン層を除去し、前記隙間(72)に施栓した前記シリコン層(74)が後に残るようにするサブステップとを有する。
互いに反対側に位置した第1と第2の主表面を有し、高濃度ドープ領域よりも上方に低濃度ドープ領域を有するシリコン半導体本体を有し、前記低濃度ドープ領域と前記高濃度ドープ領域の両方は、第1の導電型を呈するようドープされ、
前記第1の主表面から前記第2の主表面に向かって前記低濃度ドープ領域を通って前記高濃度ドープ領域の方へ延びたトレンチを有し、
前記トレンチ内のボイドの上方で前記トレンチの頂部を塞ぐシリコン栓を有し、
前記半導体デバイスの動作状態において前記低濃度ドープ領域を空乏化させて前記低濃度ドープ領域が前記動作状態における電圧に耐えることができるようにする構造体を有する半導体デバイスに関する。
Claims (13)
- 半導体デバイスの製造方法であって、
(a) 互いに反対側に位置した第1と第2の主表面を有し、高濃度ドープ領域よりも上方の第1の主表面のところに低濃度ドープ領域を有するシリコン半導体本体を用意するステップを有し、前記低濃度ドープ領域と前記高濃度ドープ領域の両方は、第1の導電型を呈するようドープされ、前記低濃度ドープ領域は、前記高濃度ドープ領域よりもドーピング度が低く、
(b) 前記第1の主表面上に開口部を備えたマスクを形成するステップを有し、
(c) 前記マスクの前記開口部を通ってトレンチを形成するステップを有し、前記トレンチは、前記第1の主表面から前記第2の主表面に向かって前記低濃度ドープ領域を通って前記高濃度ドープ領域の方へ延びており、
(d) 前記トレンチの側壁及び底部並びに前記第1の主表面にトレンチ絶縁層を被着させるステップを有し、
(e) 前記トレンチ絶縁層を前記第1の主表面に隣接して位置する前記トレンチの前記側壁の頂部から除去し、後に露出状態のシリコンが前記トレンチの前記側壁の前記頂部のところに残されるようにするステップを有し、
(f) シリコンを前記露出シリコン上で選択的に成長させてシリコンを前記トレンチの前記頂部のところで成長させ、前記トレンチの前記頂部に施栓するステップを有する方法であって、
該方法は、前記半導体デバイスの動作状態において前記低濃度ドープ領域(4)を欠乏化させて前記低濃度ドープ領域が前記動作状態における電圧に耐えることができるようにする構造体を形成するステップを更に有する、方法。 - 前記トレンチ絶縁層の被着前に、前記トレンチの前記側壁を前記第1の導電型とは反対の第2の導電型を呈するようにドープして、前記低濃度ドープ領域を欠乏化させる前記構造体を形成するステップを更に有する、請求項1に記載の方法。
- (g) 前記第1の導電型とは反対の第2の導電型のものであるようにドープされた半導体の本体領域を前記第1の主表面のところ又はこれに隣接すると共に前記トレンチに隣接して形成するステップを更に有する、請求項1又は2に記載の方法。
- (h) 第1の導電型のものであるようドープされた半導体のソース領域を前記第1の主表面のところ又はこれに隣接すると共に前記本体領域と接触して形成するステップと、
(i) 前記ソース領域とドレインとして働く前記高濃度ドープ領域との間における前記本体領域中の導通状態を制御する絶縁ゲートを形成するステップとを更に有する、請求項3に記載の方法。 - 前記ステップ(e)は、前記トレンチ絶縁層を前記トレンチの底部及び前記第1の主表面並びに前記第1の主表面に隣接した前記トレンチの前記側壁の前記頂部から除去するようオーバーエッチングし、後に前記露出シリコンが前記トレンチの前記側壁の前記頂部及び前記トレンチの前記底部のところに残るようにするステップから成る、請求項1〜4のうちいずれか一に記載の方法。
- 半絶縁性ポリシリコンを前記トレンチの前記側壁上に成膜して前記低濃度ドープ領域を欠乏化させる前記構造体を形成するステップを更に有する、請求項1〜5のうちいずれか一に記載の方法。
- 前記ステップ(c)の後に、
外側トレンチ絶縁層を前記トレンチの前記側壁及び底部に被着させるステップと、
前記外側トレンチ絶縁層を前記トレンチの前記底部から除去するステップとを有し、
次いで、半絶縁性ポリシリコンを前記トレンチ内に成膜する前記ステップを実施し、次にトレンチ絶縁層を被着させる前記ステップ(d)を実施し、
前記オーバーエッチングステップ(e)は、前記外側トレンチ絶縁層、前記半絶縁性ポリシリコン及び前記トレンチ絶縁層をエッチングして前記第1の主表面に隣接した前記トレンチの前記側壁を露出させる1又は2以上のエッチングステップを含む、請求項6記載の方法。 - 前記ステップ(f)では、
シリコンを前記トレンチの前記頂部のところの露出状態にある前記側壁上で選択的に成長させて、互いに反対側の側壁上で成長したシリコン相互間に隙間が後に残るようにし、
シリコン層を前記第1の主表面に被着させて前記トレンチの前記隙間に施栓し、
前記第1の主表面に被着させた前記シリコン層を除去し、前記隙間に施栓した前記シリコン層が後に残るようにする、請求項1〜7のうちいずれか一に記載の方法。 - 半導体デバイスであって、
互いに反対側に位置した第1と第2の主表面を有し、高濃度ドープ領域よりも上方に低濃度ドープ領域を有するシリコン半導体本体を有し、前記低濃度ドープ領域と前記高濃度ドープ領域の両方は、第1の導電型を呈するようドープされ、
前記第1の主表面から前記第2の主表面に向かって前記低濃度ドープ領域を通って前記高濃度ドープ領域の方へ延びたトレンチを有し、
前記トレンチ内のボイドの上方で前記トレンチの頂部を塞ぐシリコン栓を有し、
前記半導体デバイスの動作状態において前記低濃度ドープ領域を欠乏化させて前記低濃度ドープ領域が前記動作状態における電圧に耐えることができるようにする構造体を有し、
能動領域及び該能動領域の周りに位置するエッジ終端領域を有し、複数の前記トレンチは、前記エッジ終端領域中にエッジ終端構造体を形成し、前記第1の導電型とは反対の第2の導電型のものであるようにドープされたエッジ本体領域は、前記エッジ終端領域中の前記トレンチ相互間に延び、前記エッジ終端領域中の前記トレンチ内の前記シリコン栓は、前記トレンチの各側の前記エッジ本体領域相互間に高抵抗経路を形成するようアンドープされている、半導体デバイス。 - 前記トレンチの前記側壁に隣接した前記半導体は、前記低濃度ドープ領域を欠乏化させる構造体を形成する第2の導電型のものであるようにドープされている、請求項9記載の半導体デバイス。
- 前記トレンチの前記側壁に沿って延び、前記低濃度ドープ領域を欠乏化させる前記構造体を形成する半絶縁性ポリシリコンの層を更に有し、該半絶縁性ポリシリコンは、前記トレンチの下に位置する前記半導体及び前記トレンチの頂部のところに位置する前記シリコン栓と電気的接触状態にある、請求項9又は10に記載の半導体デバイス。
- 前記能動領域中のシリコン栓で塞がれた複数の前記トレンチを有し、前記能動領域中の前記トレンチ内の前記シリコン栓は、導電性であるようにドープされている、請求項11に記載の半導体デバイス。
- 前記第1の導電型とは逆の第2の導電型のものであるようにドープされていて、前記第1の主表面のところ又はこれに隣接すると共に前記トレンチに隣接して設けられた半導体の本体領域と、
第1の導電型のものであるようドープされていて、前記第1の主表面のところ又はこれに隣接すると共に前記本体領域と接触して設けられた半導体のソース領域と、
前記ソース領域とドレインとして働く高濃度ドープ領域との間における前記本体領域中の導通状態を制御する絶縁ゲートとを有する、請求項9〜12のうちいずれか一に記載の半導体デバイス。
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