JP4932153B2 - 複数膜厚を有する半導体相互接続の形成方法 - Google Patents

複数膜厚を有する半導体相互接続の形成方法 Download PDF

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Publication number
JP4932153B2
JP4932153B2 JP2004508382A JP2004508382A JP4932153B2 JP 4932153 B2 JP4932153 B2 JP 4932153B2 JP 2004508382 A JP2004508382 A JP 2004508382A JP 2004508382 A JP2004508382 A JP 2004508382A JP 4932153 B2 JP4932153 B2 JP 4932153B2
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Japan
Prior art keywords
layer
opening
dielectric layer
current carrying
interconnect
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Expired - Fee Related
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JP2004508382A
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English (en)
Japanese (ja)
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JP2005525000A5 (https=
JP2005525000A (ja
Inventor
シー． ユー、キャスリーン
ジェイ． ストロゼウスキー、カーク
ファーカス、ジェイノス
サンチェス、ヘクター
ティ． リー、ヨン−ジ
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004508382A 2002-05-09 2003-04-15 複数膜厚を有する半導体相互接続の形成方法 Expired - Fee Related JP4932153B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/141,714 2002-05-09
US10/141,714 US6815820B2 (en) 2002-05-09 2002-05-09 Method for forming a semiconductor interconnect with multiple thickness
PCT/US2003/012089 WO2003100825A2 (en) 2002-05-09 2003-04-15 Multiple thickness semiconductor interconnect and method therefor

Publications (3)

Publication Number Publication Date
JP2005525000A JP2005525000A (ja) 2005-08-18
JP2005525000A5 JP2005525000A5 (https=) 2006-05-11
JP4932153B2 true JP4932153B2 (ja) 2012-05-16

Family

ID=29399731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004508382A Expired - Fee Related JP4932153B2 (ja) 2002-05-09 2003-04-15 複数膜厚を有する半導体相互接続の形成方法

Country Status (7)

Country Link
US (2) US6815820B2 (https=)
JP (1) JP4932153B2 (https=)
KR (1) KR101045473B1 (https=)
CN (1) CN100397613C (https=)
AU (1) AU2003247343A1 (https=)
TW (1) TWI293493B (https=)
WO (1) WO2003100825A2 (https=)

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US7784010B1 (en) * 2004-06-01 2010-08-24 Pulsic Limited Automatic routing system with variable width interconnect
DE102006025405B4 (de) * 2006-05-31 2018-03-29 Globalfoundries Inc. Verfahren zur Herstellung einer Metallisierungsschicht eines Halbleiterbauelements mit unterschiedlich dicken Metallleitungen
CN100452063C (zh) * 2006-06-07 2009-01-14 清华大学 硅集成电路衬底多频率点下综合耦合参数的快速提取方法
US7566651B2 (en) 2007-03-28 2009-07-28 International Business Machines Corporation Low contact resistance metal contact
US8026170B2 (en) * 2007-09-26 2011-09-27 Sandisk Technologies Inc. Method of forming a single-layer metal conductors with multiple thicknesses
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US20120299187A1 (en) * 2011-05-27 2012-11-29 Broadcom Corporation Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products
US8906801B2 (en) * 2012-03-12 2014-12-09 GlobalFoundries, Inc. Processes for forming integrated circuits and integrated circuits formed thereby
US8813012B2 (en) 2012-07-16 2014-08-19 Synopsys, Inc. Self-aligned via interconnect using relaxed patterning exposure
KR102385454B1 (ko) * 2015-09-24 2022-04-08 엘지디스플레이 주식회사 휘도가 개선된 표시장치
CN107481918B (zh) * 2016-06-08 2020-04-07 中芯国际集成电路制造(上海)有限公司 芯片的制备方法及刻蚀方法
US10651201B2 (en) 2017-04-05 2020-05-12 Samsung Electronics Co., Ltd. Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging
KR102442096B1 (ko) 2017-11-22 2022-09-07 삼성전자주식회사 반도체 장치
EP3671821B1 (en) * 2018-12-19 2025-03-19 IMEC vzw Interconnection system of an integrated circuit
US12334392B2 (en) * 2019-08-07 2025-06-17 Intel Corporation Multi-height interconnect trenches for resistance and capacitance optimization
US20210043567A1 (en) * 2019-08-07 2021-02-11 Intel Corporation Place-and-route resistance and capacitance optimization using multi-height interconnect trenches and air gap dielectrics
US11195792B2 (en) 2020-01-10 2021-12-07 International Business Machines Corporation Top via stack
US12575397B2 (en) * 2022-02-25 2026-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal lines of hybrid heights
CN119581415B (zh) * 2025-01-26 2025-05-13 全智芯(上海)技术有限公司 用于调整互连线结构的方法、设备和介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685071A (ja) * 1992-08-31 1994-03-25 Fujitsu Ltd 半導体装置の製造方法
JPH09321046A (ja) * 1996-06-03 1997-12-12 Nec Corp 半導体装置およびその製造方法
JPH10200075A (ja) * 1996-11-14 1998-07-31 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000077407A (ja) * 1998-08-28 2000-03-14 Toshiba Corp 半導体装置及びその製造方法
WO2000021128A1 (en) * 1998-10-01 2000-04-13 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication

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US5286675A (en) * 1993-04-14 1994-02-15 Industrial Technology Research Institute Blanket tungsten etchback process using disposable spin-on-glass
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
JP2923912B2 (ja) * 1996-12-25 1999-07-26 日本電気株式会社 半導体装置
US6107189A (en) * 1997-03-05 2000-08-22 Micron Technology, Inc. Method of making a local interconnect using spacer-masked contact etch
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US6258727B1 (en) * 1998-07-31 2001-07-10 International Business Machines Corporation Method of forming metal lands at the M0 level with a non selective chemistry
KR20000027538A (ko) * 1998-10-28 2000-05-15 김영환 반도체 소자의 금속 배선 형성 방법
FR2786609B1 (fr) 1998-11-26 2003-10-17 St Microelectronics Sa Circuit integre a capacite interlignes reduite et procede de fabrication associe
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US6361402B1 (en) 1999-10-26 2002-03-26 International Business Machines Corporation Method for planarizing photoresist
US6451697B1 (en) 2000-04-06 2002-09-17 Applied Materials, Inc. Method for abrasive-free metal CMP in passivation domain
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Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH0685071A (ja) * 1992-08-31 1994-03-25 Fujitsu Ltd 半導体装置の製造方法
JPH09321046A (ja) * 1996-06-03 1997-12-12 Nec Corp 半導体装置およびその製造方法
JPH10200075A (ja) * 1996-11-14 1998-07-31 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000077407A (ja) * 1998-08-28 2000-03-14 Toshiba Corp 半導体装置及びその製造方法
WO2000021128A1 (en) * 1998-10-01 2000-04-13 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication

Also Published As

Publication number Publication date
AU2003247343A8 (en) 2003-12-12
US6815820B2 (en) 2004-11-09
CN100397613C (zh) 2008-06-25
US20050035459A1 (en) 2005-02-17
WO2003100825A3 (en) 2004-04-15
KR101045473B1 (ko) 2011-06-30
AU2003247343A1 (en) 2003-12-12
JP2005525000A (ja) 2005-08-18
TW200406870A (en) 2004-05-01
US20030209779A1 (en) 2003-11-13
KR20050007531A (ko) 2005-01-19
TWI293493B (en) 2008-02-11
WO2003100825A2 (en) 2003-12-04
CN1653607A (zh) 2005-08-10
US7176574B2 (en) 2007-02-13

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