JP4907256B2 - 半導体ヘテロ構造、および半導体ヘテロ構造を形成する方法 - Google Patents
半導体ヘテロ構造、および半導体ヘテロ構造を形成する方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 70
- 238000000034 method Methods 0.000 title claims description 37
- 239000000758 substrate Substances 0.000 claims description 61
- 229910052710 silicon Inorganic materials 0.000 claims description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- 230000003746 surface roughness Effects 0.000 claims description 39
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 27
- 239000000203 mixture Substances 0.000 claims description 26
- 229910052732 germanium Inorganic materials 0.000 claims description 24
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 20
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 19
- 230000007547 defect Effects 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000002040 relaxant effect Effects 0.000 claims 1
- 238000005389 semiconductor device fabrication Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 26
- 239000000463 material Substances 0.000 description 18
- 239000002243 precursor Substances 0.000 description 15
- 238000000151 deposition Methods 0.000 description 14
- 230000008021 deposition Effects 0.000 description 9
- 239000002131 composite material Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 238000009499 grossing Methods 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 150000004820 halides Chemical class 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 239000010421 standard material Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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Description
Claims (22)
- 第1の面内格子パラメータa1を有する基板(2)を提供するステップと、
第2の面内格子パラメータa2を有するバッファ層(3)を設けるステップと、
前記バッファ層(3)の上に上部層(6)を設けるステップとを含む、半導体ヘテロ構造を形成する方法であって、
追加層(5)が前記バッファ層(3)と前記上部層(6)の間に設置され、前記追加層(5)がそれを超えると欠陥が発生する限界厚さ未満の厚さを有する歪み層であって、前記第1および第2の格子パラメータa1とa2の間である第3の面内格子パラメータa3を有し、それによって前記上部層(6)の表面粗さを改善し、前記基板および前記バッファ層の前記各格子パラメータが、それぞれ緩和状態の格子パラメータ値に相当し、後続層に対する境界面での格子パラメータであることを特徴とする
方法。 - 前記追加層(5)および/または前記上部層(6)を、前記バッファ層(3)の成長温度よりも低い成長温度で成長させる、請求項1に記載の方法。
- 前記追加層(5)および/または前記上部層(6)の成長温度が、前記バッファ層(3)の成長温度よりも50〜500℃低くなるように選択される、請求項2に記載の方法。
- 前記追加層(5)の厚さが、1000Å未満である、請求項1〜3のいずれかに記載の方法。
- 前記バッファ層(3、13)および前記追加層(5)が、少なくとも2種の化合物AとBとを含み、互いに異なる組成A1−xa2Bxa2およびA1−xa3Bxa3を有する、請求項1〜4のいずれか一項に記載の方法。
- 組成の差Δx=xa2−xa3 が0.5〜8%である、請求項5に記載の方法。
- 前記上部層(6)が歪み層または緩和層であり、シリコン(sSi)、シリコンゲルマニウム(Si1−xGex)、およびゲルマニウム(Ge)のうちの1つである、請求項1〜6のいずれか一項に記載の方法。
- 前記基板(12)がシリコンであり、および/または前記バッファ層(3、13)がシリコンゲルマニウム(Si1−xa2Gexa2)である、請求項1〜7のいずれか一項に記載の方法。
- 前記追加層(5)がシリコンゲルマニウム(Si1−xa3Gexa3)である、請求項1〜8のいずれか一項に記載の方法。
- 前記上部層(6)用に使用されるときのシリコンの成長温度が600℃未満になるように選択され、あるいは前記上部層(6)用に使用される場合のゲルマニウムの成長温度が500℃未満になるように選択される、請求項7に記載の方法。
- 第1の面内格子パラメータa1を有する基板(2)と、
第2の面内格子パラメータa2を有するバッファ層(3)と、
前記バッファ層(3)の上に上部層(6)とを備える、半導体ヘテロ構造であって、
追加層(5)が前記バッファ層(3)と前記上部層(6)の間にあり、前記追加層(5)がそれを超えると欠陥が発生する限界厚さ未満の厚さを有する歪み層であって、前記第1と第2の格子パラメータの間である第3の面内格子パラメータa3を有し、前記各層の前記各格子パラメータが、それぞれ緩和状態の格子パラメータ値に相当し、後続層に対する境界面での格子パラメータであることを特徴とする、
半導体ヘテロ構造。 - 前記上部層(6)の表面粗さが1.8ÅRMS未満である、請求項11に記載の半導体ヘテロ構造。
- 前記追加層(5)と前記上部層(6)の間の境界面での境界面粗さが2.5ÅRMS未満である、請求項11または12に記載の半導体ヘテロ構造。
- 前記バッファ層(3)および前記追加層(5)が、少なくとも2種の化合物AとBとを含み、互いに異なる組成A1−xa2Bxa2およびA1−xa3Bxa3を有する、請求項11〜13のいずれか一項に記載の半導体ヘテロ構造。
- 組成の差Δx=xa2−xa3 が0.5〜8%である、請求項14に記載の半導体ヘテロ構造。
- 前記追加層(5)および/または前記上部層の厚さが、1000Å未満である、請求項11〜15のいずれか一項に記載の半導体ヘテロ構造。
- 前記基板(2、12)がシリコンであり、および/または前記バッファ層(3、13)がシリコンゲルマニウム(Si1−xa2Gexa2)であり、および/または前記上部層(6)が歪み層または緩和層であり、歪みシリコン(sSi)、シリコンゲルマニウム(Si1−xGex)、およびゲルマニウム(Ge)のうちの1つであり、および/または前記追加層がシリコンゲルマニウム(Si1−xa3Gexa3)である、請求項11〜16のいずれか一項に記載の半導体ヘテロ構造。
- 請求項11〜17のいずれか一項に記載の半導体ヘテロ構造の、半導体デバイスの製作プロセス中での基板としての使用。
- 請求項11〜17のいずれか一項に記載の半導体ヘテロ構造の、歪み層オンインシュレータウェハの製作プロセス中での使用。
- 前記製作プロセスがスマートカット式プロセスであり、請求項11〜17のいずれか一項に記載の半導体ヘテロ構造がドナー基板として使用される、請求項18に記載の半導体ヘテロ構造の使用。
- 請求項11〜17のいずれか一項に記載の半導体ヘテロ構造を備える半導体デバイス。
- ウェハと、その一方の表面にあり、請求項11〜17のいずれか一項に記載の半導体ヘテロ構造から前記ウェハ上に移転された歪みSi層とを備え、前記上部層(6)が歪みシリコン層であり、前記歪みシリコン層(6)と前記追加層(5)の間の元からの埋込み境界面(7)がsSOIウェハの自由面に対応する、歪みシリコンオンインシュレータウェハ(sSOI)。
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EP05291841.4 | 2005-09-07 | ||
EP05291841.4A EP1763069B1 (en) | 2005-09-07 | 2005-09-07 | Method for forming a semiconductor heterostructure |
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JP4907256B2 true JP4907256B2 (ja) | 2012-03-28 |
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US (2) | US7772127B2 (ja) |
EP (1) | EP1763069B1 (ja) |
JP (1) | JP4907256B2 (ja) |
KR (1) | KR100832152B1 (ja) |
CN (1) | CN101140864B (ja) |
SG (2) | SG150571A1 (ja) |
TW (1) | TWI343650B (ja) |
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US7785995B2 (en) * | 2006-05-09 | 2010-08-31 | Asm America, Inc. | Semiconductor buffer structures |
JP5380794B2 (ja) | 2007-06-22 | 2014-01-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法および半導体層の形成方法 |
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