JP4889464B2 - 電子部品の実装方法 - Google Patents

電子部品の実装方法 Download PDF

Info

Publication number
JP4889464B2
JP4889464B2 JP2006331245A JP2006331245A JP4889464B2 JP 4889464 B2 JP4889464 B2 JP 4889464B2 JP 2006331245 A JP2006331245 A JP 2006331245A JP 2006331245 A JP2006331245 A JP 2006331245A JP 4889464 B2 JP4889464 B2 JP 4889464B2
Authority
JP
Japan
Prior art keywords
electrode
substrate
electronic component
alignment protrusion
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006331245A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008147317A (ja
JP2008147317A5 (https=
Inventor
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2006331245A priority Critical patent/JP4889464B2/ja
Publication of JP2008147317A publication Critical patent/JP2008147317A/ja
Publication of JP2008147317A5 publication Critical patent/JP2008147317A5/ja
Application granted granted Critical
Publication of JP4889464B2 publication Critical patent/JP4889464B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2006331245A 2006-12-08 2006-12-08 電子部品の実装方法 Expired - Fee Related JP4889464B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006331245A JP4889464B2 (ja) 2006-12-08 2006-12-08 電子部品の実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006331245A JP4889464B2 (ja) 2006-12-08 2006-12-08 電子部品の実装方法

Publications (3)

Publication Number Publication Date
JP2008147317A JP2008147317A (ja) 2008-06-26
JP2008147317A5 JP2008147317A5 (https=) 2009-11-05
JP4889464B2 true JP4889464B2 (ja) 2012-03-07

Family

ID=39607181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006331245A Expired - Fee Related JP4889464B2 (ja) 2006-12-08 2006-12-08 電子部品の実装方法

Country Status (1)

Country Link
JP (1) JP4889464B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11769702B2 (en) 2020-04-15 2023-09-26 Murata Manufacturing Co., Ltd. Amplifier module

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165872A (ja) * 2010-02-09 2011-08-25 Renesas Electronics Corp Ｂｇａタイプ半導体装置の接続構造
JP5481249B2 (ja) 2010-03-26 2014-04-23 富士通株式会社 半導体装置及びその製造方法
JP5927756B2 (ja) * 2010-12-17 2016-06-01 ソニー株式会社 半導体装置及び半導体装置の製造方法
WO2014182239A1 (en) * 2013-05-07 2014-11-13 Smartflex Technology Pte Ltd Ultra-thin smart card modules with chip bumps disposed in susbtrate via holes and methods of fabricating the same
EP2819162B1 (en) 2013-06-24 2020-06-17 IMEC vzw Method for producing contact areas on a semiconductor substrate
JP2015149314A (ja) * 2014-02-04 2015-08-20 富士通株式会社 半導体装置及びその製造方法
CN109309069A (zh) * 2018-09-19 2019-02-05 深圳市心版图科技有限公司 焊球阵列封装芯片及其焊接方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170444A (ja) * 1988-12-22 1990-07-02 Matsushita Electric Works Ltd 半導体素子の実装方法
JPH03218039A (ja) * 1990-01-23 1991-09-25 Sumitomo Electric Ind Ltd 半導体素子の実装方法
JPH04199524A (ja) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp 半導体装置
JP2715793B2 (ja) * 1992-03-19 1998-02-18 日本電気株式会社 半導体装置及びその製造方法
JPH10256308A (ja) * 1997-03-06 1998-09-25 Oki Electric Ind Co Ltd 半導体チップ実装構造及びその実装方法
JPH11111772A (ja) * 1997-10-07 1999-04-23 Matsushita Electric Ind Co Ltd キャリア基板の実装位置決め方法、キャリア基板および配線基板
JPH11163194A (ja) * 1997-11-26 1999-06-18 Oki Electric Ind Co Ltd Ｖｌｓｉパッケージ
JP2002246512A (ja) * 2001-02-16 2002-08-30 Nec Corp Ｂｇａパッケージの構造及び実装基板の構造
JP2002373914A (ja) * 2001-06-15 2002-12-26 Ricoh Co Ltd 電子部品接続構造体
JP2006324577A (ja) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11769702B2 (en) 2020-04-15 2023-09-26 Murata Manufacturing Co., Ltd. Amplifier module

Also Published As

Publication number Publication date
JP2008147317A (ja) 2008-06-26

Similar Documents

Publication Publication Date Title
JP5606695B2 (ja) 接続端子付き基板
US8697492B2 (en) No flow underfill
JP5713598B2 (ja) ソケット及びその製造方法
US20140291865A1 (en) Electronic apparatus and fabrication method of the same
JP2009545180A (ja) 半導体フリップチップパッケージ用の基板およびプロセス
JP4568215B2 (ja) 回路装置および回路装置の製造方法
JP2010277829A (ja) 接続端子付き基板
US9837337B2 (en) Wiring substrate, method of manufacturing the same and electronic component device
US7893550B2 (en) Semiconductor package comprising alignment members
JP4889464B2 (ja) 電子部品の実装方法
WO2018220998A1 (ja) 半導体装置および半導体装置の製造方法
JP4240899B2 (ja) 半導体装置及び半導体装置の製造方法
EP3301712A1 (en) Semiconductor package assembley
JP5187714B2 (ja) 半導体チップの電極接続構造
JP3878436B2 (ja) 配線基板および半導体装置
JP5794833B2 (ja) 接続端子及びその製造方法、並びにソケット
JPH11340277A (ja) 半導体チップ搭載基板、半導体装置及び前記半導体チップ搭載基板への半導体チップ搭載方法
US7315086B2 (en) Chip-on-board package having flip chip assembly structure and manufacturing method thereof
CN216120289U (zh) 电子器件
JP2005353854A (ja) 配線基板およびそれを用いた半導体装置
JP2008118152A (ja) 半導体装置および積層型半導体装置
US10483195B2 (en) Resin board, method of manufacturing resin board, circuit board, and method of manufacturing circuit board
JP4072693B2 (ja) 半導体装置の製造方法
KR100791575B1 (ko) 테이프캐리어형 반도체 장치
CN100499054C (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080430

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090903

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091014

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110830

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111026

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111115

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111213

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141222

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees