JP4889359B2 - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
JP4889359B2
JP4889359B2 JP2006111661A JP2006111661A JP4889359B2 JP 4889359 B2 JP4889359 B2 JP 4889359B2 JP 2006111661 A JP2006111661 A JP 2006111661A JP 2006111661 A JP2006111661 A JP 2006111661A JP 4889359 B2 JP4889359 B2 JP 4889359B2
Authority
JP
Japan
Prior art keywords
main surface
electronic device
electrode pads
frame
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006111661A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007287820A5 (https=
JP2007287820A (ja
Inventor
稔 篠原
了 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006111661A priority Critical patent/JP4889359B2/ja
Publication of JP2007287820A publication Critical patent/JP2007287820A/ja
Publication of JP2007287820A5 publication Critical patent/JP2007287820A5/ja
Application granted granted Critical
Publication of JP4889359B2 publication Critical patent/JP4889359B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/24Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2006111661A 2006-04-14 2006-04-14 電子装置 Expired - Fee Related JP4889359B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006111661A JP4889359B2 (ja) 2006-04-14 2006-04-14 電子装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006111661A JP4889359B2 (ja) 2006-04-14 2006-04-14 電子装置

Publications (3)

Publication Number Publication Date
JP2007287820A JP2007287820A (ja) 2007-11-01
JP2007287820A5 JP2007287820A5 (https=) 2009-04-23
JP4889359B2 true JP4889359B2 (ja) 2012-03-07

Family

ID=38759327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006111661A Expired - Fee Related JP4889359B2 (ja) 2006-04-14 2006-04-14 電子装置

Country Status (1)

Country Link
JP (1) JP4889359B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783805A (zh) * 2017-03-13 2017-05-31 中国科学院微电子研究所 射频多芯片封装及屏蔽电路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987872B2 (en) * 2013-03-11 2015-03-24 Qualcomm Incorporated Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages
WO2014208010A1 (ja) * 2013-06-25 2014-12-31 パナソニックIpマネジメント株式会社 マイクロ波回路
JP2025119873A (ja) 2024-02-02 2025-08-15 キヤノン株式会社 電子モジュール及び電子機器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63128736A (ja) * 1986-11-19 1988-06-01 Olympus Optical Co Ltd 半導体素子
JP4078033B2 (ja) * 1999-03-26 2008-04-23 株式会社ルネサステクノロジ 半導体モジュールの実装方法
JP2001111232A (ja) * 1999-10-06 2001-04-20 Sony Corp 電子部品実装多層基板及びその製造方法
JP2002043507A (ja) * 2000-07-31 2002-02-08 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP4045083B2 (ja) * 2000-12-25 2008-02-13 株式会社ルネサステクノロジ 半導体モジュールおよび実装構造体
KR100521279B1 (ko) * 2003-06-11 2005-10-14 삼성전자주식회사 적층 칩 패키지
JP2005005092A (ja) * 2003-06-11 2005-01-06 Sony Corp 電子回路装置及び接続部材
JP3842272B2 (ja) * 2004-06-02 2006-11-08 株式会社Genusion インターポーザー、半導体チップマウントサブ基板および半導体パッケージ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783805A (zh) * 2017-03-13 2017-05-31 中国科学院微电子研究所 射频多芯片封装及屏蔽电路

Also Published As

Publication number Publication date
JP2007287820A (ja) 2007-11-01

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