JP4889359B2 - 電子装置 - Google Patents
電子装置 Download PDFInfo
- Publication number
- JP4889359B2 JP4889359B2 JP2006111661A JP2006111661A JP4889359B2 JP 4889359 B2 JP4889359 B2 JP 4889359B2 JP 2006111661 A JP2006111661 A JP 2006111661A JP 2006111661 A JP2006111661 A JP 2006111661A JP 4889359 B2 JP4889359 B2 JP 4889359B2
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- electronic device
- electrode pads
- frame
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111661A JP4889359B2 (ja) | 2006-04-14 | 2006-04-14 | 電子装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111661A JP4889359B2 (ja) | 2006-04-14 | 2006-04-14 | 電子装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007287820A JP2007287820A (ja) | 2007-11-01 |
| JP2007287820A5 JP2007287820A5 (https=) | 2009-04-23 |
| JP4889359B2 true JP4889359B2 (ja) | 2012-03-07 |
Family
ID=38759327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006111661A Expired - Fee Related JP4889359B2 (ja) | 2006-04-14 | 2006-04-14 | 電子装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4889359B2 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783805A (zh) * | 2017-03-13 | 2017-05-31 | 中国科学院微电子研究所 | 射频多芯片封装及屏蔽电路 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
| WO2014208010A1 (ja) * | 2013-06-25 | 2014-12-31 | パナソニックIpマネジメント株式会社 | マイクロ波回路 |
| JP2025119873A (ja) | 2024-02-02 | 2025-08-15 | キヤノン株式会社 | 電子モジュール及び電子機器 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63128736A (ja) * | 1986-11-19 | 1988-06-01 | Olympus Optical Co Ltd | 半導体素子 |
| JP4078033B2 (ja) * | 1999-03-26 | 2008-04-23 | 株式会社ルネサステクノロジ | 半導体モジュールの実装方法 |
| JP2001111232A (ja) * | 1999-10-06 | 2001-04-20 | Sony Corp | 電子部品実装多層基板及びその製造方法 |
| JP2002043507A (ja) * | 2000-07-31 | 2002-02-08 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
| JP4045083B2 (ja) * | 2000-12-25 | 2008-02-13 | 株式会社ルネサステクノロジ | 半導体モジュールおよび実装構造体 |
| KR100521279B1 (ko) * | 2003-06-11 | 2005-10-14 | 삼성전자주식회사 | 적층 칩 패키지 |
| JP2005005092A (ja) * | 2003-06-11 | 2005-01-06 | Sony Corp | 電子回路装置及び接続部材 |
| JP3842272B2 (ja) * | 2004-06-02 | 2006-11-08 | 株式会社Genusion | インターポーザー、半導体チップマウントサブ基板および半導体パッケージ |
-
2006
- 2006-04-14 JP JP2006111661A patent/JP4889359B2/ja not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783805A (zh) * | 2017-03-13 | 2017-05-31 | 中国科学院微电子研究所 | 射频多芯片封装及屏蔽电路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007287820A (ja) | 2007-11-01 |
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