JP4860189B2 - 半導体メモリ素子の金属配線形成方法 - Google Patents
半導体メモリ素子の金属配線形成方法 Download PDFInfo
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- JP4860189B2 JP4860189B2 JP2005165549A JP2005165549A JP4860189B2 JP 4860189 B2 JP4860189 B2 JP 4860189B2 JP 2005165549 A JP2005165549 A JP 2005165549A JP 2005165549 A JP2005165549 A JP 2005165549A JP 4860189 B2 JP4860189 B2 JP 4860189B2
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- Prior art keywords
- insulating film
- interlayer insulating
- drain contact
- contact plug
- forming
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- 238000000034 method Methods 0.000 title claims description 85
- 229910052751 metal Inorganic materials 0.000 title claims description 50
- 239000002184 metal Substances 0.000 title claims description 50
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 239000011229 interlayer Substances 0.000 claims description 73
- 238000005530 etching Methods 0.000 claims description 43
- 150000004767 nitrides Chemical class 0.000 claims description 31
- 239000000243 solution Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 21
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
11、111 トンネル酸化膜
12、112 フローティングゲート
13、113 誘電体膜
14、114 コントロールゲート
15、115 導電層
16、116 ゲート電極
17、117 スペーサ
18、118 絶縁膜
19、119 第1層間絶縁膜
20 ソースコンタクトホール
21、120 ソースコンタクトプラグ
22、121 第2層間絶縁膜
23、122 ドレインコンタクトプラグ
24、123 窒化膜
25、125 第3層間絶縁膜
26、125 トレンチマスク
27、126 トレンチ
28、127 金属配線
Claims (10)
- (a)ソースコンタクトプラグの形成された半導体基板を提供する段階と、
(b)前記半導体基板上に第1層間絶縁膜を形成する段階と、
(c)ドレインコンタクトマスクを用いたエッチング工程によって前記第1層間絶縁膜をパターニングし、前記半導体基板内に形成されたドレイン領域を露出させるドレインコンタクトホールを形成する段階と、
(d)前記ドレインコンタクトホールが埋め立てられるようにドレインコンタクトプラグを形成する段階と、
(e)第1エッチング工程によって前記第1層間絶縁膜をリセスさせて前記ドレインコンタクトプラグを突出させる段階と、
(f)前記ドレインコンタクトプラグを含む全体構造上の段差に沿って窒化膜を蒸着する段階と、
(g)前記窒化物上に第2層間絶縁膜を形成する段階と、
(h)前記ドレインコンタクトプラグの突出部位に形成された前記窒化膜が露出するように前記第2層間絶縁膜をパターニングしてトレンチを形成する段階と、
(i)第2エッチング工程によって前記トレンチを介して露出する前記窒化膜を除去して前記ドレインコンタクトプラグを露出させる段階と、
(j)前記トレンチが埋め立てられるように金属配線を形成する段階とを含むことを特徴とする半導体メモリ素子の金属配線形成方法。 - 前記第1エッチング工程は、前記第1層間絶縁膜が前記ドレインコンタクトプラグより少なくとも3倍以上速いエッチング速度でエッチングされるように、条件を設定することを特徴とする請求項1記載の半導体メモリ素子の金属配線形成方法。
- 前記第1エッチング工程はBOEまたはDHF溶液を用いて行うことを特徴とする請求項1または2記載の半導体メモリ素子の金属配線形成方法。
- 前記BOE溶液は、前記第1層間絶縁膜がPE−TEOS膜で形成される場合、100:1〜9:1の割合でH2Oによって希釈されたHFとNH4Fの混合溶液を使用することを特徴とする請求項3記載の半導体メモリ素子の金属配線形成方法。
- 前記DHF溶液は、前記第1層間絶縁膜がPE−TEOS膜で形成される場合、100:1〜50:1の割合でH2Oによって希釈されたHF溶液を使用することを特徴とする請求項3記載の半導体メモリ素子の金属配線形成方法。
- 前記(e)段階で、前記ドレインコンタクトプラグは300Å〜1000Åに突出することを特徴とする請求項1記載の半導体メモリ素子の金属配線形成方法。
- 前記第2エッチング工程はドライエッチングまたはウェットエッチング方式で行うことを特徴とする請求項1記載の半導体メモリ素子の金属配線形成方法。
- 前記ドライエッチング方式は、CF4、CHF3、O2及びArガスを含む混合ガスを用いて行うことを特徴とする請求項7記載の半導体メモリ素子の金属配線形成方法。
- 前記ウェットエッチング方式は、H3PO4溶液を用いて40Å/min〜60Å/minのエッチング速度で行うことを特徴とする請求項7記載の半導体メモリ素子の金属配線形成方法。
- 前記第2エッチング工程は、前記ドレインコンタクトプラグの周辺部に蒸着された前記第2層間絶縁膜が前記窒化膜の上部から200Å〜300Åの厚さにリセスされるように行うことを特徴とする請求項1または7記載の半導体メモリ素子の金属配線形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-0084475 | 2004-10-21 | ||
KR1020040084475A KR100546936B1 (ko) | 2004-10-21 | 2004-10-21 | 반도체 메모리 소자의 금속배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006121038A JP2006121038A (ja) | 2006-05-11 |
JP4860189B2 true JP4860189B2 (ja) | 2012-01-25 |
Family
ID=36129085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005165549A Expired - Fee Related JP4860189B2 (ja) | 2004-10-21 | 2005-06-06 | 半導体メモリ素子の金属配線形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7262122B2 (ja) |
JP (1) | JP4860189B2 (ja) |
KR (1) | KR100546936B1 (ja) |
DE (1) | DE102005022371B4 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100680465B1 (ko) * | 2005-06-30 | 2007-02-08 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US20070202688A1 (en) * | 2006-02-24 | 2007-08-30 | Pei-Yu Chou | Method for forming contact opening |
KR100849066B1 (ko) * | 2007-02-06 | 2008-07-30 | 주식회사 하이닉스반도체 | 실린더형 엠아이엠 캐패시터 형성방법 |
JP4504403B2 (ja) * | 2007-08-29 | 2010-07-14 | 株式会社東芝 | 半導体記憶装置 |
US7662645B2 (en) * | 2007-09-06 | 2010-02-16 | United Microelectronics Corp. | Reworked integrated circuit device and reworking method thereof |
US20090302477A1 (en) * | 2008-06-06 | 2009-12-10 | Yakov Shor | Integrated circuit with embedded contacts |
US11276637B2 (en) * | 2019-09-17 | 2022-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier-free interconnect structure and manufacturing method thereof |
US11177163B2 (en) * | 2020-03-17 | 2021-11-16 | International Business Machines Corporation | Top via structure with enlarged contact area with upper metallization level |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08306787A (ja) * | 1995-03-06 | 1996-11-22 | Sanyo Electric Co Ltd | 半導体装置及び半導体装置の製造方法 |
JPH09223735A (ja) * | 1996-02-15 | 1997-08-26 | Sony Corp | 半導体装置のコンタクト開孔方法 |
JP3235542B2 (ja) * | 1997-10-15 | 2001-12-04 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6331481B1 (en) * | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
US6083842A (en) * | 1999-02-19 | 2000-07-04 | Advanced Micro Devices Inc. | Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug |
JP2001196477A (ja) * | 2000-01-14 | 2001-07-19 | Toshiba Corp | 半導体装置 |
JP3532134B2 (ja) * | 2000-01-31 | 2004-05-31 | シャープ株式会社 | 半導体装置の製造方法 |
JP2001358214A (ja) * | 2000-06-15 | 2001-12-26 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2002076297A (ja) * | 2000-08-28 | 2002-03-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP4074054B2 (ja) * | 2000-09-28 | 2008-04-09 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP4128737B2 (ja) * | 2000-11-14 | 2008-07-30 | 株式会社東芝 | 半導体装置及び半導体記憶装置の製造方法 |
US6680514B1 (en) * | 2000-12-20 | 2004-01-20 | International Business Machines Corporation | Contact capping local interconnect |
US6294426B1 (en) * | 2001-01-19 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole |
KR100395766B1 (ko) * | 2001-02-12 | 2003-08-25 | 삼성전자주식회사 | 강유전체 기억 소자 및 그 형성 방법 |
JP2002343861A (ja) * | 2001-05-21 | 2002-11-29 | Mitsubishi Electric Corp | 半導体集積回路およびその製造方法 |
JP2003023102A (ja) * | 2001-07-05 | 2003-01-24 | Mitsubishi Electric Corp | キャパシタの製造方法 |
JP2003249578A (ja) * | 2001-09-29 | 2003-09-05 | Toshiba Corp | 半導体集積回路装置 |
JP2003249572A (ja) * | 2001-12-19 | 2003-09-05 | Mitsubishi Electric Corp | 半導体装置の製造方法及び半導体装置 |
KR100434505B1 (ko) * | 2002-06-19 | 2004-06-05 | 삼성전자주식회사 | 다마신 배선을 이용한 반도체 소자의 제조방법 |
KR100434511B1 (ko) * | 2002-08-12 | 2004-06-05 | 삼성전자주식회사 | 다마신 배선을 이용한 반도체 소자의 제조방법 |
-
2004
- 2004-10-21 KR KR1020040084475A patent/KR100546936B1/ko not_active IP Right Cessation
-
2005
- 2005-05-10 DE DE102005022371A patent/DE102005022371B4/de not_active Expired - Fee Related
- 2005-06-06 JP JP2005165549A patent/JP4860189B2/ja not_active Expired - Fee Related
- 2005-06-06 US US11/146,171 patent/US7262122B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006121038A (ja) | 2006-05-11 |
KR100546936B1 (ko) | 2006-01-26 |
US7262122B2 (en) | 2007-08-28 |
DE102005022371B4 (de) | 2013-02-28 |
US20060088991A1 (en) | 2006-04-27 |
DE102005022371A1 (de) | 2006-04-27 |
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