JP4825529B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4825529B2
JP4825529B2 JP2006027830A JP2006027830A JP4825529B2 JP 4825529 B2 JP4825529 B2 JP 4825529B2 JP 2006027830 A JP2006027830 A JP 2006027830A JP 2006027830 A JP2006027830 A JP 2006027830A JP 4825529 B2 JP4825529 B2 JP 4825529B2
Authority
JP
Japan
Prior art keywords
holes
hole
wiring board
semiconductor device
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006027830A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007208153A (ja
JP2007208153A5 (https=
Inventor
好彦 嶋貫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006027830A priority Critical patent/JP4825529B2/ja
Publication of JP2007208153A publication Critical patent/JP2007208153A/ja
Publication of JP2007208153A5 publication Critical patent/JP2007208153A5/ja
Application granted granted Critical
Publication of JP4825529B2 publication Critical patent/JP4825529B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2006027830A 2006-02-06 2006-02-06 半導体装置 Expired - Fee Related JP4825529B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006027830A JP4825529B2 (ja) 2006-02-06 2006-02-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006027830A JP4825529B2 (ja) 2006-02-06 2006-02-06 半導体装置

Publications (3)

Publication Number Publication Date
JP2007208153A JP2007208153A (ja) 2007-08-16
JP2007208153A5 JP2007208153A5 (https=) 2009-03-19
JP4825529B2 true JP4825529B2 (ja) 2011-11-30

Family

ID=38487328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006027830A Expired - Fee Related JP4825529B2 (ja) 2006-02-06 2006-02-06 半導体装置

Country Status (1)

Country Link
JP (1) JP4825529B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4998338B2 (ja) * 2008-03-11 2012-08-15 富士通セミコンダクター株式会社 半導体装置及び回路基板
JP5223571B2 (ja) 2008-09-30 2013-06-26 富士通株式会社 半導体装置、基板設計方法、基板設計装置
JP5557439B2 (ja) 2008-10-24 2014-07-23 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
WO2014208010A1 (ja) 2013-06-25 2014-12-31 パナソニックＩｐマネジメント株式会社 マイクロ波回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3685347B2 (ja) * 1995-12-30 2005-08-17 ソニー株式会社 半導体装置
JPH113954A (ja) * 1997-06-11 1999-01-06 Hitachi Cable Ltd 半導体素子搭載用配線基板および半導体装置
JP2002118204A (ja) * 1999-11-17 2002-04-19 Sumitomo Bakelite Co Ltd 半導体装置、並びに半導体搭載用基板及びその製造方法
JP3936681B2 (ja) * 2003-08-25 2007-06-27 沖電気工業株式会社 半導体装置
JP4308608B2 (ja) * 2003-08-28 2009-08-05 株式会社ルネサステクノロジ 半導体装置
JP4273895B2 (ja) * 2003-09-24 2009-06-03 日立化成工業株式会社 半導体素子搭載用パッケージ基板の製造方法

Also Published As

Publication number Publication date
JP2007208153A (ja) 2007-08-16

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