JP4816314B2 - Storage element and storage device - Google Patents

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

  However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device. The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power. In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

  However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced. For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor. A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is a glass material or a semiconductor material made of a solid solution of chalcogenide and metal, and more specifically, a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe ( For example, a chalcogenide glass containing Cu, Ag, Zn such as AsSAg, GeSeAg, GeSAg, AsSCu, GeSeCu, GeSCu is suitable. Cu, Ag, and Zn are contained (see Patent Document 1).

The other electrode is formed of tungsten, nickel, molybdenum, platinum, metal silicide, or the like that does not substantially dissolve in the material containing the ion conductor.
For example, a memory cell can be formed by connecting a memory element and a selection element such as a diode or a MOS transistor, and arranging the memory cell in an array.

  In the memory element having this configuration, by applying a bias voltage equal to or higher than the threshold voltage to the two electrodes, conductive ions (ions such as Cu, Ag, and Zn) in the ion conductor move in the negative electrode direction, Electrodeposition occurs by reaching the negative electrode. Furthermore, since this electrodeposition grows in dendrites, for example, and reaches the positive electrode, a current path is formed, so that the resistance value of the ion conductor changes from high resistance to low resistance. Thereby, information can be recorded in the memory element.

  In addition, by applying a voltage of opposite polarity to the above bias voltage to the two electrodes, the conductive ions that formed the dendritic current path are dissolved in the ion conductor, so that the current path disappears. Then, the resistance value returns to the initial high resistance state. Thereby, the recorded information is erased.

  However, in the memory element having a structure in which Ag or Cu is contained in either the upper electrode or the lower electrode and a Ge—S or Ge—Se amorphous chalcogenide material is sandwiched between the electrodes, the chalcogenide thin film is formed by the temperature rise. Crystallization occurs. And the characteristics of the material change with this crystallization, and there is a problem that the part that originally holds data in a high resistance state changes to a low resistance state in a high temperature environment or during long-term storage. .

  Therefore, a memory element having a configuration in which a rare earth oxide film is inserted between the electrode and the ion conductor as a barrier layer that restricts the movement of ions between the ion conductor and the electrode has been proposed (for example, Patent Documents). 2).

  In the memory element having the barrier layer formed of the rare earth oxide film as described above, Cu, Ag, Zn is ionized from the electrode layer containing Cu, Ag, Zn by applying a recording voltage higher than the threshold voltage. Then, it diffuses into the rare earth oxide film and is combined with electrons on the other electrode side to be deposited, or stays diffused inside the rare earth oxide film. Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the rare earth oxide thin film, or a large number of defects due to Cu, Ag, Zn are formed inside the rare earth oxide thin film. The resistance value of becomes low.

  Further, by applying a voltage having a polarity opposite to that described above, Cu, Ag, and Zn constituting the current path or impurity level formed in the rare earth oxide film are ionized again and move in the rare earth oxide film. Returning to the electrode layer side, the resistance value of the rare earth oxide film increases.

  It has been reported that the memory element based on the resistance change of the rare earth oxide film has excellent characteristics, particularly in a high temperature environment and for long-term data retention, even when miniaturized.

Special Table 2002-536840 Publication Nikkei Electronics January 20, 2003 issue (page 104) JP 2005-197634 A

  However, in the above-described memory element in which either the upper electrode or the lower electrode contains Cu, Ag, Zn and Ge—S or Ge—Se amorphous chalcogenide material is sandwiched between these electrodes, the ion source layer includes The contained Cu, Ag, Zn easily diffuses into the rare earth oxide film and the interlayer insulating layer in an external high temperature environment, and it is difficult to maintain a high resistance state even during long-term data storage. Has occurred.

For example, when a current for reading information is supplied to a memory element in which the current path disappears and the resistance value is in a high resistance state, instantaneously about 1000 ° C. with respect to the inside of the memory element It is predicted by calculation that the heat of is added.
In this way, a large amount of heat is generated in the element by repeatedly passing a current through the memory element.

Conventionally, SiO ₂ that has been used as an interlayer insulating film is susceptible to diffusion of conductive ions. Therefore, when a large amount of heat is generated in the element by repeatedly flowing a current through the memory element, Cu and Ag contained in the source layer diffuse into the interlayer insulating film.
For this reason, it is difficult to maintain a high resistance state, and it is considered that information is deteriorated.

  In order to solve the above-described problems, the present invention provides a highly reliable memory element and a recording apparatus using the same, which can stably hold information recorded on a memory thin film. .

The memory element of the present invention is configured by sandwiching an insulating layer and a memory layer between a first electrode and a second electrode, and the memory layer includes a memory thin film and ionized Cu, Ag, or Zn. And the storage thin film is made of a rare earth element oxide, the storage layer and one electrode are connected through an opening formed in the insulating layer, and the insulating layer is The thermal conductivity is 15 W / mK or more, and the insulating layer has a film thickness of 10 nm or more.

  A memory device of the present invention includes the memory element of the present invention, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. Is.

  According to the configuration of the memory element of the present invention described above, the memory layer is sandwiched between the first electrode and the second electrode, and this memory layer is ionized on the memory thin film. By stacking an ion source layer containing Cu, Ag, or Zn, information can be stored by utilizing the change in the resistance state of the memory thin film included in the memory layer.

Specifically, for example, when a positive potential is applied to one electrode on the side of the ion source layer containing Cu and a positive voltage is applied to the memory element, Cu contained in the ion source layer is ionized and stored. The resistance value of the memory thin film can be reduced by diffusing into the thin film and bonding and depositing with electrons at the other electrode side, or by remaining in the memory thin film and forming an impurity level of the insulating layer. This lowers the resistance value of the memory layer including the memory thin film, which makes it possible to write information.
Further, from this state, when a negative potential is applied to one electrode on the ion source layer side and a negative voltage is applied to the memory element, Cu deposited on the other electrode side is ionized again, and one electrode side Since the resistance value of the memory layer returns to the original high state and the resistance value of the memory element increases, the recorded information can be erased.

Further, since the memory layer and the one electrode are connected through the opening formed in the insulating layer, the insulating layer defines a contact area between the memory layer and the electrode. By using an insulating material having a thermal conductivity of 15 W / mK or more as the insulating layer, heat applied to the memory element can be radiated by the insulating material having high thermal conductivity in a high temperature environment. It is.
For this reason, it is possible to suppress diffusion of Cu, Ag, Zn, and the like contained in the ion source layer in a high-temperature environment into the memory thin film, the insulating layer, and the like due to heat.

According to the memory element of the present invention described above, the retention characteristics of information recorded on the memory thin film can be improved even in a high temperature environment.
In addition, by using the memory element of the present invention, a memory device excellent in stability and durability can be configured.

  FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a memory element 10 as an embodiment of the present invention.

In the memory element 10, for example, a lower electrode 1 that is a connection portion with a CMOS circuit portion is formed on a silicon substrate 11 (see FIG. 3) on which a CMOS circuit is formed, and an opening is formed on the lower electrode 1. An insulating layer 2 having a portion and a memory layer 6 are formed, and an upper electrode 5 is formed on the memory layer 6.
The lower electrode 1 and the memory layer 6 are connected through an opening formed in the insulating layer 2.

  For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, WN, TaN, silicide, or the like can be used.

  For the upper electrode 5, similarly to the lower electrode 1, a wiring material used in a normal semiconductor process can be used.

For the insulating layer 2, an insulating material having a thermal conductivity of 15 W / mK or more, for example, silicon nitride, aluminum oxide, silicon carbide, or the like can be used. Specifically, Si ₃ N ₄ , Al ₂ O ₃ SiC or the like can be used.
The area of the opening formed in the insulating layer 2 is not particularly limited. For example, as shown in FIG. 1, an opening corresponding to only a part of the area of the lower electrode 1 may be formed, and when the lower electrode is sufficiently small, the area of the lower electrode and the opening The area may be the same.
The insulating layer 2 is formed with a film thickness of 10 nm or more, for example. Thus, the heat applied to the storage element 10, it is possible to ing to efficiently released without lowering other properties.

The memory layer 6 includes a memory thin film 3 and an ion source layer 4 formed on the memory thin film 3.
The ion source layer 4 contains an ionizing element (ion source element), that is, Cu, Ag, or Zn, and more preferably contains Te, Se, and S chalcogenide elements.

The memory thin film 3 is made of an oxide of one or more elements (rare earth elements) selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y. It is formed.
The memory thin film 3 is formed with a film thickness of about 0.5 nm to 10 nm, for example. Thus, by reducing the film thickness of the memory thin film 3, it is possible to pass a current through the memory thin film 3 made of a rare earth oxide or the like, which is usually an insulating material.
The actual memory cell portion is determined by the area where the lower electrode 1 and the recording thin film 3 are in contact.

The ion source layer 4 is, for example, a film having a composition in which Cu, Ag, Zn is added to GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, etc. containing a chalcogenide element of Te, Se, S, Ag film, Ag An alloy film, a Cu film, a Cu alloy film, a Zn film, a Zn alloy film, or the like can be used.
In addition, heat resistance can be improved by adding Ge, rare earth elements, etc. to this ion source layer 4 as needed.

  The memory element 10 made of the above-described material has a characteristic that impedance (resistance value) changes when a voltage pulse or a current pulse is applied. The memory thin film 3 has a sufficiently larger change in resistance value than the other layers of the memory element 10. Therefore, the change in the resistance value of the entire memory element 10 is mainly influenced by the memory thin film 3. Therefore, information can be recorded in the memory element 10 by utilizing the change in the resistance value of the memory thin film 3.

In the memory element 10 of the above-described embodiment, the insulating layer, the oxide layer 31 and the memory thin film 3 are formed on the lower electrode 1, and the ion source layer 4 is stacked on the memory thin film 3. It is said.
However, the ion source layer 4 containing Cu, Ag, or Zn and the memory thin film 3 are sequentially stacked on the lower electrode 1 to form the memory layer 3, and the insulating layer 2 and the upper electrode 5 are formed thereon. Such a configuration of the stacking order opposite to that of the memory element 10 of the above-described embodiment can also be employed.

  The storage element 10 of this embodiment can be operated as follows to store information.

  First, a voltage is applied to the storage element 10 so that the upper electrode 5 side in contact with the ion source layer 4 containing Cu, Ag or Zn is positive, and the lower electrode 1 side in contact with the recording thin film 3 is negative. . Here, the voltage applied to the memory element 10 at this time is defined as a positive voltage (+), and the same definition is described below.

By applying a positive voltage to the memory element 10, Cu, Ag or Zn is ionized from the ion source layer 4, diffuses in the memory thin film 3, and bonds with electrons on the lower electrode 1 side to be deposited. Alternatively, it remains diffused inside the memory thin film 3.
Then, a current path containing a large amount of Cu, Ag, or Zn is formed inside the memory thin film 3, or a large number of defects due to Cu, Ag, or Zn are formed inside the memory thin film 3, whereby the memory thin film The resistance value of 3 becomes low.
Each layer other than the memory thin film 3 originally has a lower resistance value than the resistance value of the memory thin film 3 before recording. Therefore, by reducing the resistance value of the memory thin film 3, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by this process (recording process).

Further, when applied to a storage device such as a RAM or an EEPROM, an erasing process for returning the storage element 10 to a high resistance state is necessary. In this erasing process, a negative voltage (−) is applied to the memory element 10 so that the upper electrode 5 side is negative and the lower electrode 1 side is positive.
By applying a negative voltage to the memory element 10, Cu, Ag or Zn constituting the current path or impurity level formed in the memory thin film 3 is ionized and moves in the memory thin film 3. Return to the ion source layer 4 side.

  Then, the current path or defect due to Cu, Ag, or Zn disappears from the memory thin film 3, and the resistance value of the memory thin film 3 increases. Since each layer other than the memory thin film 3 originally has a low resistance value, the resistance value of the memory element 10 as a whole can be increased by increasing the resistance value of the memory thin film 3.

  After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.
That is, binary information can be stored depending on the resistance value of the memory element 10.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the memory thin film 3, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio between the initial resistance value and the resistance value after recording is approximately twice or more. If the resistance value before recording is 100Ω, the resistance value after recording is 50Ω, or if the resistance value before recording is 100 kΩ, the resistance value after recording is 50 kΩ. The initial resistance value of the thin film 3 is set so as to satisfy such a condition. The resistance value of the memory thin film 3 can be controlled, for example, by changing the thickness of the memory thin film 3.

According to the memory element 10 described above, the memory thin film 3 and the ion source layer 4 are sandwiched between the lower electrode 1 and the upper electrode 5. With this configuration, for example, when a positive voltage (+ potential) is applied to the ion source layer 4 side containing Cu, Ag, or Zn so that the lower electrode 1 side becomes negative, the inside of the memory thin film 3 In addition, a current path containing a large amount of Cu, Ag or Zn is formed. Thereby, the resistance value of the memory thin film 3 is lowered, and the resistance value of the entire memory element 10 is lowered.
Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded.

  Since information is stored by utilizing a change in the resistance value of the memory element 10, particularly a change in the resistance value of the memory thin film 3, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

In the erasing operation, a negative voltage (−potential) is applied to the upper electrode 5 on the ion source layer 4 side containing Cu, Ag, or Zn to the memory element 10 in the post-recording state as described above for memory. The lower electrode 1 side on the thin film 3 side is made positive.
As a result, the current path formed by Cu, Ag, or Zn formed in the memory thin film 3 disappears, the resistance value of the memory thin film 3 is increased, and the resistance value of the entire memory element 10 is increased.
Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

  Further, by forming the insulating layer 2 using a material having high thermal conductivity between the lower electrode 1 and the memory layer 6 of the memory element 10 described above, Cu, Ag in the ion source layer under a high temperature environment. Alternatively, Zn can be prevented from diffusing into the memory thin film 3 and the insulating layer 2.

  Therefore, even when information writing and erasing and information reading are repeatedly performed during long-term data storage, the heat applied to the memory element 10 can be dissipated by the insulating layer. For this reason, the memory element 10 can stably store long-term data even in a high temperature environment.

  Specifically, the memory element 10 of the present embodiment can be manufactured as follows, for example.

  First, a lower electrode 1 made of, for example, W is formed on a substrate on which a CMOS circuit such as a selection transistor is formed. Thereafter, if necessary, oxides on the plug surface are removed by reverse sputtering or the like.

Next, after forming an insulating film made of, for example, Si ₃ N _{4 on} the lower electrode 1, an opening for contacting the lower electrode 1 and the memory layer 6 is formed. The portions other than the portion are covered with a mask, and the insulating film is selectively etched. At this time, for example, the opening is circular and has a diameter of 30 nm.
Thereby, the insulating layer 2 is formed.

Next, after forming a gadolinium film with a film thickness of, for example, 3 nm using, for example, a gadolinium target in the upper part of the insulating layer 2 and the opening formed in the insulating layer 2, the gadolinium film is oxidized by oxygen plasma. .
Thereby, the memory thin film 3 is formed.

Next, a GeTeGd film, for example, is formed on the memory thin film 3 by DC magnetron sputtering.
Thereby, the ion source layer 4 is formed.

  Next, for example, a W film is formed on the ion source layer 4 to form the upper electrode 5.

  Thereafter, the insulating layer 2, the memory thin film 3, the ion source layer 4 and the upper electrode 5 are patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).

  Next, a wiring layer connected to the upper electrode 5 is formed to connect the memory element 10 and a contact for obtaining a common potential.

  In this way, the memory element 10 can be manufactured.

A storage device (memory device) can be configured by arranging a large number of the memory elements 10 having the above-described configuration on a matrix.
FIG. 2 shows a schematic configuration diagram (perspective view) of one embodiment of such a storage device.

In this storage device, for each storage element 10, a plurality of word lines WL connected to the lower electrode 1 side and a plurality of bit lines BL installed on the upper electrode 5 side orthogonal to the word lines WL are provided. The memory element 10 is arranged at each intersection of the word line WL and the bit line BL.
A large number of memory cells 20 formed in this way are arranged to form a memory cell array.
The memory device shown in FIG. 2 shows a memory cell array having a configuration in which 3 × 3 memory cells 20 are arranged in a matrix.

  In such a storage device, by configuring the storage device using the storage element 10 having the above-described configuration, fluctuations in the resistance value during recording and erasing are reduced. For this reason, data deterioration is reduced particularly when the repetitive operation is performed, and information can be read stably. Accordingly, it is possible to realize a storage device with stable operation and high reliability.

Further, for example, it is conceivable to form a memory device by forming wirings connected to the upper electrode 5 in common for the entire memory cell array.
3 and 4 are schematic configuration diagrams of one embodiment of the memory cell array configured as described above. 3 is a cross-sectional view, and FIG. 4 is a plan view.

  As shown in FIGS. 3 and 4, in this memory cell array, the memory element 10 constituting each memory cell includes the insulating layer 2, the memory thin film 3, the ion source layer 4, and the upper electrode 5 over the entire memory cell. Share. In other words, each memory element 10 is composed of the same insulating layer 2, memory thin film 3, ion source layer 4, and upper electrode 5.

The upper electrode 5 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. A memory element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 3, each storage element 10 constituting each memory cell of the memory cell array is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the memory element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. This metal wiring layer 16 is connected to a bit line BL (see FIG. 4) which is the other address wiring of the memory element.

  In FIG. 4, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 4, reference numeral 21 indicates a contact portion that communicates with the lower electrode 1 of the memory element 10, and 22 indicates a contact portion that communicates with the bit line BL.

The memory cell array shown in FIGS. 3 and 4 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.

Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 5 (plate electrode PL), the resistance value of the memory element 10 transitions to a low resistance state. To do. Thereby, information can be recorded in the memory element 10 of the selected memory cell.
Further, by applying a field voltage, which is a positive potential compared to the potential of the upper electrode 5 (plate electrode PL), to the lower electrode 1, the resistance value of the memory element 10 transitions again to the high resistance state. Thereby, the recorded information can be erased from the storage element 10 of the selected memory cell.

In order to read out recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the memory element 10 is changed. Different currents or voltages are detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the memory element 10 changes.

  According to the memory element 10 of the above-described embodiment, information can be easily recorded and read out, and in particular, it has excellent characteristics such that variations in write and erase voltage thresholds are small.

  Further, even when the storage device of the above-described embodiment is miniaturized, it is easy to record information and hold recorded information. Therefore, by configuring the storage device using the storage element 10 of the above-described embodiment, the storage device can be integrated (high density) or downsized.

(Example)
Next, the memory element 10 described above was actually fabricated and its characteristics were evaluated.
In an actual memory device, as shown in FIGS. 2 to 4, memory elements are arranged in an array, or there are circuit elements such as transistors in addition to the memory element portion. The test device (characteristic evaluation element) shown in Fig. 1 was prepared, and the characteristics were measured and evaluated.
FIG. 5A shows a plan view of the manufactured test device, and FIG. 5B shows a cross-sectional view taken along the line AA ′ of the test device of FIG. 5A. With this test device, the read resistance margin of the memory element was examined, and the characteristics of the characteristic evaluation test device were measured and evaluated.

In this characteristic evaluation test device, a lower electrode 1 common to the memory element 10 of each memory cell is formed on a silicon substrate. The memory layer 6 including the memory thin film 3 and the ion source layer 4 of the memory element 10 is connected to the lower electrode 1 through the opening of the insulating layer 2 on the lower electrode 1.
Further, the portion where the memory layer 6 and the lower electrode 1 are connected becomes the memory cell 20, and the shape of this portion is circular as shown in FIG. 5A.

  The storage layer 6 of the storage element 10 includes the periphery of the memory cell 20 and is formed in the vertically long element formation region 23 shown in FIG. 5A. The upper electrode 5 is formed vertically long along the element formation region 23. Lower electrode connection terminal pads 24 are formed on the left and right sides of the element formation region 23, and upper electrode connection terminal pads 25 are formed on both ends of the upper electrode 5.

Example 1
First, a 100 nm thick W film as the lower electrode 1 and a 10 nm thick SiC film as the insulating layer 2 were sequentially formed on a 2 mm thick silicon substrate.
Thereafter, by using photolithography, the insulating layer 2 was selectively etched by covering the openings of the insulating layer 2 to be the memory cells 20 and the portions other than the connection terminal pads 24 of the lower electrode 1 with a mask. At this time, the planar shape of the portion to be the memory cell 20, that is, the opening of the insulating layer 2 on the lower electrode 1, was circular, and its diameter was 30 nm.

  Next, a gadolinium oxide film with a thickness of 3 nm is formed as the memory thin film 3 and a CuGeTeGd film with a thickness of 20 nm and a Cu film with a thickness of 12 nm are sequentially formed as the ion source layer 4 so as to cover the opening of the insulating layer 2. A laminated film to be the memory layer 6 of the memory element 10 was formed.

Next, the memory layer 6 is masked by using photolithography to mask a range of 200 μm by 600 μm, which is a region where the memory element 10 is formed, and then the memory layer 6 (3, 4) is formed by Ar plasma. Etched.
Furthermore, after masking using photolithography except for the portions to be the upper electrode 5, the lower electrode connecting terminal pad 24, and the upper electrode connecting terminal pad 25, an electrode material is formed by DC magnetron sputtering. did. Then, the mask was removed by a known lift-off method to form an upper electrode 5, a lower electrode connecting terminal pad 24, and an upper electrode connecting terminal pad 25, each of which was made of an electrode material.
As the upper electrode 5, the lower electrode connecting terminal pad 24, and the upper electrode connecting terminal pad 25, a laminated film of a Cr film having a thickness of 20 nm, a Cu film having a thickness of 100 nm, and an Au film having a thickness of 100 nm was formed. .

  In this way, a test device for evaluating the characteristics of the memory element 10 was produced by a known etching and lithography technique.

(Example 2)
A test device for characteristic evaluation of Example 2 was produced in the same manner as in Example 1 except that the insulating layer 2 was formed using Al ₂ O ₃ having a thickness of 10 nm.

(Example 3)
A test device for characteristic evaluation of Example 3 was produced in the same manner as in Example 1 except that the insulating layer 2 was formed using Si ₃ N ₄ having a thickness of 10 nm.

(Comparative Example 1)
The characteristics of Comparative Example 1 were evaluated in the same manner as in Example 1 except that the insulating layer 2 was formed using a laminated film of ZrO ₂ having _a thickness of 5 nm and Al ₂ O ₃ having a thickness of 5 nm. A test device was fabricated.

(Comparative Example 2)
A test device for evaluating characteristics of Comparative Example 2 was produced in the same manner as in Example 1 except that the insulating layer 2 was formed using MgO having a thickness of 10 nm.

(Comparative Example 3)
A test device for characteristic evaluation of Comparative Example 3 was produced in the same manner as in Example 1 except that the insulating layer 2 was formed using SiO ₂ having a thickness of 10 nm.

(Characteristic evaluation)
1000 test devices prepared in Examples 1 to 3 and Comparative Examples 1 to 3 were manufactured, and after performing continuous information writing and erasing operations 1000 times for all of them, the resistance at the time of recording and erasing information Was measured under an external environment of 160 ° C. for 20 hours, and the recording resistance retention ratio and the erasure resistance retention ratio of each test device were obtained.
In addition, the resistance retention rate of each test device was calculated | required with the following formula | equation.
Resistance holding ratio (%) = (160 ° C., number of elements whose resistance change after test for 20 hours was within 10% / 1000) × 100

Table 1 shows the resistance retention rate of each test device determined by the above formula and the thermal conductivity of the material used as the insulating layer of each test device.
FIG. 6 shows the relationship between the recording resistance retention ratio and the erasure resistance retention ratio of each test device and the thermal conductivity of the insulating material used as the insulating layer of each test device. In FIG. 6, the vertical axis indicates the resistance retention rate (%), and the horizontal axis indicates the thermal conductivity (W / mK).

According to Table 1, the test devices of Examples 1 to 3 showed good recording resistance retention and erasure resistance retention. On the other hand, in the test devices of Comparative Examples 1 to 3, the recording resistance retention rate and the erasure resistance retention rate are lower than those of the test devices of Examples.
That is, it can be seen that the higher the thermal conductivity of the material used for the insulating layer, the higher the data retention rate during recording and erasing.
In particular, the erase resistance retention ratios of the test devices of Comparative Examples 1 to 3 are greatly reduced as compared with the test devices of the examples. This is presumably because, under high temperature conditions, Cu in the ion source layer 4 diffuses into the memory thin film 3 and the resistance value of the test device decreases, so that the erasure resistance retention ratio decreases.

Further, according to FIG. 6, it is found that the thermal conductivity is required to be 15 W / mK or more in order to make the erase resistance change 5% or less (erase resistance retention ratio 95% or more).
Therefore, in order to improve the data retention rate at the time of recording and erasure and improve the retention characteristic of information recorded in the storage layer in a high temperature environment, the insulating layer has a thermal conductivity of 15 W / mK or more. It is necessary to use materials.

  A memory device (memory device) can be formed by arranging a large number of memory elements, for example, in a column shape or a matrix shape, using the memory element of the present invention described above. Further, a memory cell can be configured by connecting a MOS transistor or a diode for selecting an element to each memory element 10 as necessary. Furthermore, it can be connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, and the like via wiring.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. Any memory form such as a memory) can be applied.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element of the present invention. It is a schematic block diagram (perspective view) of the memory | storage device using the memory element of FIG. It is a schematic block diagram (sectional drawing) of the memory cell array using the memory element of FIG. FIG. 2 is a schematic configuration diagram (plan view) of a memory cell array using the memory element of FIG. 1. It is a schematic block diagram (plan view) of a test device for A characteristic evaluation. It is a schematic block diagram (sectional drawing) of the test device for B characteristic evaluation. It is a figure which shows the relationship between the heat conductivity of an insulating film, and resistance retention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Insulating layer, 3 Memory thin film, 4 Ion source layer, 5 Upper electrode, 6 Memory layer, 10 Memory element, 11 Semiconductor substrate, 12 Element isolation layer, 13 Source / drain region, 14 Gate electrode, 15 Plug layer, 16 Metal wiring layer, 17 Plug layer, 18 Active area, 20 Memory cell, 23 Element formation area, 24 Lower electrode connection terminal pad, 25 Upper electrode connection terminal pad, BL bit line, PL plate electrode, Tr MOS transistor, WL Word line

Claims (7)

An insulating layer and a memory layer are sandwiched between the first electrode and the second electrode,
The memory layer is formed by stacking a memory thin film and an ion source layer containing ionized Cu, Ag, or Zn,
The memory thin film is made of a rare earth element oxide,
The memory layer and one electrode are connected through an opening formed in the insulating layer,
The insulating layer is composed of one or more selected from silicon nitride, aluminum oxide and silicon carbide having a thermal conductivity of 15 W / mK or more ,
The thickness of the insulating layer is 10 nm or more
Serial憶素Ko. The ion source layer, Te, Se, memory element according to 請 Motomeko 1 it contains one or more elements selected from S. The insulating layer, the memory device according to configured請 Motomeko 1 of silicon carbide. The memory element according to claim 3, wherein the insulating layer is made of SiC . Wherein the storage layer by applying a voltage pulse or a current pulse, said impedance of the storage layer is changed, the memory device according to 請 Motomeko 1 recorded Ru done information. An insulating layer and a memory layer are sandwiched between the first electrode and the second electrode, and the memory layer includes a memory thin film and an ion source layer containing ionized Cu, Ag, or Zn. The memory thin film is made of a rare earth element oxide, the memory layer and one electrode are connected through an opening formed in the insulating layer, and the insulating layer is thermally conductive. A memory element having a rate of 15 W / mK or more selected from silicon nitride, aluminum oxide, and silicon carbide, wherein the insulating layer has a thickness of 10 nm or more ;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device comprising a large number of the storage elements. In the adjacent plurality of memory elements, storage device according to 請 Motomeko 6 at least part of the layer that is formed commonly by the same layer forming the storage element.

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