JP4760606B2 - Storage element and storage device - Google Patents

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element with a reduction in the size of memory elements that constitute each memory cell.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, and Zn are dissolved in AsS, GeS, GeSe, and one of the two electrodes. The electrode contains Cu, Ag, and Zn (see Patent Document 1).

The other electrode is formed of W, Ni, Mo, Pt, metal silicide, or the like that does not substantially dissolve in the material containing the ionic conductor.
For example, a memory cell can be formed by connecting a memory element and a selection element such as a diode or a MOS transistor, and arranging the memory cell in an array.

  In the memory element of this configuration, by applying a bias voltage equal to or higher than the threshold voltage to the two electrodes, conductive ions (ions such as Ag, Cu, Zn, etc.) in the ion conductor move in the negative electrode direction, Electrodeposition occurs by reaching the negative electrode. Furthermore, since this electrodeposition grows in dendrites, for example, and reaches the positive electrode, a current path is formed, so that the resistance value of the ion conductor changes from high resistance to low resistance. As a result, information can be recorded (written) in the storage element.

  In addition, by applying a voltage of opposite polarity to the above bias voltage to the two electrodes, the conductive ions that formed the dendritic current path are dissolved in the ion conductor, so that the current path disappears. Then, the resistance value returns to the initial high resistance state. Thereby, the recorded information is erased.

  However, in the memory element having a structure in which Ag or Cu is contained in either the upper electrode or the lower electrode and a Ge—S or Ge—Se amorphous chalcogenide material is sandwiched between the electrodes, the chalcogenide thin film is formed by the temperature rise. Crystallization occurs, the characteristics of the material change with crystallization, and the part that originally holds the data in a high resistance state changes to a low resistance state in a high temperature environment or during long-term storage, And so on.

  Therefore, a memory element having a structure in which a rare earth oxide film is inserted as a barrier layer that restricts movement of ions between the ion conductor and the electrode between the electrode and the ion conductor has also been proposed (for example, Patent Document 2).

  In the memory element having the configuration in which the barrier layer made of the rare earth oxide film is formed in this way, Ag, Cu, or Zn contained in the electrode layer is ionized by applying a recording voltage higher than the threshold voltage, and the rare earth oxide film To spread. Then, these ions are combined with electrons on the other electrode side and deposited, or remain in a state of being diffused inside the rare earth oxide film. Then, a current path containing a large amount of the metal element is formed inside the rare earth oxide thin film, or a large number of defects due to the metal element are formed inside the rare earth oxide thin film, thereby reducing the resistance value of the rare earth oxide film. Lower.

  Further, by applying a voltage having a polarity opposite to the recording voltage described above, Ag, Cu, or Zn constituting the current path or impurity level formed in the rare earth oxide film is ionized again, and the rare earth oxide film The resistance value of the rare earth oxide film is increased by moving inside and returning to the electrode layer side.

  It has been reported that the memory element based on the resistance change of the rare earth oxide film has excellent characteristics, particularly in a high temperature environment and for long-term data retention, even when miniaturized.

Special Table 2002-536840 Publication Nikkei Electronics January 20, 2003 issue (page 104) JP 2005-197634 A

  However, in the memory element having a configuration in which a rare earth oxide film is inserted between the electrode and the ionic conductor described above, the current density flowing in the element portion increases with the miniaturization, and a local temperature rise occurs. . For this reason, Ag, Cu, or Zn contained in the electrode layer is diffused to other than the rare earth oxide film in the memory cell due to heat generated by repeated writing and erasing, and the resistance value of the memory element at the time of erasing is gradually increased. This causes a problem of lowering.

That is, while the writing and erasing are repeated in the memory element, even if the erasing operation is performed, the low resistance state remains unchanged and the high resistance state is not restored. In this case, since the storage element is short-circuited, the operation becomes impossible and an error bit is generated. This is because Ag, Cu, or Zn contained in the electrode layer diffuses to other than the rare-earth oxide film in the memory cell portion, thereby generating a current path separately from the original current path. It is done.
Further, when the threshold voltage for writing or erasing changes during the repeated operation, the memory element becomes an error bit.
Further, when writing and erasing information with the low resistance state of writing being “1” and the high resistance state of erasing being “0”, when the difference between the low resistance state and the high resistance state is reduced, “0” and “ 1 "cannot be determined.

  In order to solve the above-described problems, the present invention provides a storage element having excellent resistance to repeated writing and erasing operations and a recording apparatus using the same.

In the memory element of the present invention, a memory layer is disposed between the first electrode and the second electrode, and the memory layer includes an oxide layer made of an oxide of a rare earth element and ionizing Cu, Ag, or An ion source layer containing at least one selected from Zn, in contact with the oxide layer and the ion source layer, and around the connection portion between the oxide layer and the ion source layer, Ta, An ion source diffusion control layer that restricts ion diffusion is provided, which is made of a nitride of one or more elements selected from Ti, Nb, V, and Zr .

In the memory device of the present invention, a memory layer is disposed between the first electrode and the second electrode, and the memory layer is selected from an oxide layer made of an oxide of a rare earth element and ionized Cu, Ag, or Zn. Ta, Ti, Nb in contact with the oxide layer and the ion source layer and around the connecting portion between the oxide layer and the ion source layer. A storage element including a nitride of one or more elements selected from V, Zr, provided with an ion source diffusion control layer for regulating ion diffusion, and a wiring connected to the first electrode side; And a plurality of memory elements are arranged. The wiring is connected to the second electrode side.

  According to the configuration of the memory element of the present invention described above, the memory layer is sandwiched between the first electrode and the second electrode, and this memory layer includes the oxide layer and the ionized Cu. By including the ion source layer containing Ag, Zn or Zn, information can be stored by utilizing the change in the resistance state of the oxide layer included in the memory layer.

Specifically, for example, when a positive potential is applied to one electrode on the ion source layer side containing Cu and a positive voltage is applied to the memory element, Cu contained in the ion source layer is ionized to be an oxide. The resistance value of the oxide layer is reduced by diffusing into the layer and bonding to the electrons on the other electrode side and depositing, or by forming impurity levels in the insulating layer that remain in the oxide layer. This lowers the resistance value of the memory layer including the oxide layer, which makes it possible to write information.
Further, from this state, when a negative potential is applied to one electrode on the ion source layer side and a negative voltage is applied to the memory element, Cu deposited on the other electrode side is ionized again, and one electrode side Since the resistance value of the memory layer returns to the original high state and the resistance value of the memory element increases, the recorded information can be erased.

In addition, an ion source diffusion control layer that regulates the diffusion of ions is provided in contact with the oxide layer and the ion source layer and around the connection portion between the oxide layer and the ion source layer. The diffusion of Cu, Ag, or Zn ions when stored is restricted to the connection portion between the oxide layer and the ion source layer.
Even when information writing and erasing are repeated, Cu, Ag, or Zn ions are less likely to diffuse outside the connecting portion of the oxide layer with the ion source layer. It is possible to suppress a decrease in resistance value at the time of erasing.

According to the memory element of the present invention described above, when information writing and erasing are repeated, the resistance value at the time of erasing does not decrease, so that resistance to repeated writing and erasing operations can be improved. .
In addition, by using the memory element of the present invention, a memory device excellent in stability and durability can be configured.

  FIG. 1 shows a schematic configuration diagram (cross-sectional view) of the memory element 10 according to the first embodiment of the present invention.

  In the memory element 10 shown in FIG. 1, for example, a lower electrode 1 that is a connection portion with a CMOS circuit portion is formed on a silicon substrate 11 (see FIG. 3) on which a CMOS circuit is formed. A memory layer 2 is formed thereon, and an upper electrode 5 is formed on the memory layer 2.

  The memory layer 2 includes an oxide layer 3 and an ion source layer 4 formed on the oxide layer 3, and the ion source diffusion control layer 6 is interposed between the oxide layer 3 and the ion source layer 4. Is formed. The oxide layer 3 and the ion source layer 4 are connected through an opening formed in the ion source diffusion control layer 6.

For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, WN, TaN, silicide, or the like can be used.
For the upper electrode 5, similarly to the lower electrode 1, a wiring material used in a normal semiconductor process can be used.

The oxide layer 3 includes one or more elements (rare earth elements) selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y (rare earth elements) and oxygen. It can be configured using a material to be contained, for example, a rare earth oxide such as gadolinium oxide.
The oxide layer 3 is formed with a film thickness of about 0.5 nm to 10 nm, for example. Thus, by reducing the thickness of the oxide layer 3, it is possible to pass a current through the oxide layer 3 made of a rare earth oxide or the like, which is usually an insulating material.

  The ion source layer 4 contains Cu, Ag, or Zn, and more preferably further contains a chalcogenide element of Te, Se, and S. For example, GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, etc., Cu , Ag, Zn added film, Ag film, Ag alloy film, Cu film, Cu alloy film, Zn film, Zn alloy film, or the like. Moreover, heat resistance can be improved by adding Ge, rare earth elements, etc. to this ion source layer 4 as needed.

The ion source diffusion control layer 6 is not particularly limited as long as it can control the diffusion of Cu, Ag, or Zn ions, but a material having a low resistance value and used in a conventional semiconductor process is preferable. For example, it can be configured using a material used for a barrier metal film of a conventional semiconductor device.
As such a material, for example, a transition metal nitride can be used, and specifically, a nitrogen compound material containing at least one of Ta, Ti, Nb, V, and Zr is used. More specifically, TaN, TaSiN, TiN, NbN, VN, ZrN, or the like can be used.
The ion source diffusion control layer 6 has an opening for regulating the area and location where the ion source layer 4 is in contact with the oxide layer 3.

The oxide layer 3 made of the above-described material has a characteristic that the impedance (resistance value) changes when a voltage pulse or a current pulse is applied.
The oxide layer 3 has a sufficiently large change in resistance value than the other layers. Therefore, the change in the resistance value of the entire memory element 10 is mainly influenced by the oxide layer 3. Therefore, information can be recorded in the memory element 10 using the change in the resistance value of the oxide layer 3.

  In the memory element 10 shown in FIG. 1, the oxide layer 3 is formed below the ion source diffusion control layer 6 and the ion source layer 4 is formed on the ion source diffusion control layer 6. 3. The order of lamination may be opposite to that in FIG. 1 so that the ion source layer 4 is formed below.

  The storage element 10 of the first embodiment can be operated as follows to store information.

First, a voltage is applied to the memory element 10 so that the upper electrode 5 side in contact with the ion source layer 4 containing Cu, Ag, or Zn is positive and the lower electrode 1 side in contact with the oxide layer 3 is negative. . Here, the voltage applied to the memory element 10 at this time is defined as a positive voltage (+), and the same definition is given below.
By applying a positive voltage to the memory element 10, Cu, Ag or Zn ions are ion-conducted in the oxide layer 3 from the ion source layer 4 and are combined with electrons on the lower electrode 1 side, and are deposited. It remains in the state of diffusing inside the oxide layer 3.

  Then, a current path containing a large amount of Cu, Ag, or Zn is formed inside the oxide layer 3, or a large number of defects due to Cu, Ag, or Zn are formed inside the oxide layer 3. The resistance value of the layer 3 is lowered. Each layer other than the oxide layer 3 originally has a lower resistance value than the resistance value of the oxide layer 3 before recording. Therefore, by reducing the resistance value of the oxide layer 3, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the memory element 10 is held with the resistance value lowered. As a result, information can be recorded in the storage element 10.

  At this time, by applying a voltage to the entire oxide layer 3, ionization occurs in the ion source layer 4 within the range of the area of the lower electrode 1, and the ionized Cu, Ag, or Zn moves toward the oxide layer 3. Try to spread. However, in the present embodiment, the ion source diffusion control layer 6 is formed between the oxide layer 3 and the ion source layer 4. Therefore, when a positive voltage (+) is applied, ions can be diffused only in part of the oxide layer 3, and the ion source layer 4 of the oxide layer 3 is formed by the opening formed in the ion source diffusion control layer 6. Except for the portion connected to, the defects constituting the above-described current path or impurity level are not formed.

  When used in a storage device that can be recorded only once, so-called PROM, the storage is completed only by the recording process.

  On the other hand, when applied to a erasable storage device, a storage device such as a so-called RAM or EEPROM, an erasing process is required to return the storage element 10 to a high resistance state. In this erasing process, a negative voltage (−) is applied to the memory element 10 so that the upper electrode 5 side is negative and the lower electrode 1 side is positive.

  By applying a negative voltage to the memory element 10, Cu, Ag, or Zn constituting the current path or impurity level formed in the oxide layer 3 is ionized, and ion conduction occurs in the oxide layer 3. Then, it returns to the ion source layer 4 side.

  Then, current paths or defects due to Cu, Ag, or Zn disappear from the oxide layer 3, and the resistance value of the oxide layer 3 increases. Since each layer other than the oxide layer 3 originally has a low resistance value, the resistance value of the entire memory element 10 can be increased by increasing the resistance value of the oxide layer 3.

  After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.
That is, the binary information of “0” and “1” can be stored in the storage element 10 depending on the level of the resistance value.

The resistance value after recording depends on recording conditions such as the voltage pulse or current pulse width and current amount applied during recording, rather than the cell size of the memory element 10 and the material composition of the oxide layer 3, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio between the initial resistance value and the resistance value after recording is approximately twice or more. If the resistance value before recording is 100Ω, the resistance value after recording is 50Ω, or if the resistance value before recording is 100 kΩ, it is sufficient if the resistance value after recording is 50 kΩ. The initial resistance value of the layer 3 is set so as to satisfy such a condition. The resistance value of the oxide layer 3 can be controlled, for example, by changing the thickness of the oxide layer 3.

According to the memory element 10 described above, the oxide layer 3 and the ion source layer 4 are sandwiched between the lower electrode 1 and the upper electrode 5. With such a configuration, for example, when a positive voltage (+ potential) is applied to the ion source layer 4 side containing Cu or Ag so that the lower electrode 1 side becomes negative, the oxide layer 3 includes A current path containing a large amount of Cu, Ag or Zn is formed. Thereby, the resistance value of the oxide layer 3 is lowered, and the resistance value of the entire memory element 10 is lowered.
Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded.

  Since information is stored by using a change in the resistance value of the memory element 10, particularly a change in the resistance value of the oxide layer 3, the information recording is performed even when the memory element 10 is miniaturized. And storage of recorded information becomes easy.

Further, in the erasing operation, a negative voltage (−potential) is applied to the upper electrode 5 on the ion source layer 4 side containing Cu, Ag, or Zn with respect to the memory element 10 in the state after recording, and the oxide The lower electrode 1 side on the layer 3 side is made positive.
As a result, the current path formed by Cu, Ag, or Zn formed in the oxide layer 3 disappears, the resistance value of the oxide layer 3 increases, and the resistance value of the entire memory element 10 increases.
Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

Further, according to the memory element 10 described above, the ion source diffusion control layer 6 is formed between the ion source layer 4 and the oxide layer 3, and the connection portion between the ion source layer 4 and the oxide layer 3 is an ion. It is restricted within the opening formed in the source diffusion control layer 6. Thereby, the place where the ion from the ion source layer 4 diffuses can be controlled.
Accordingly, even when information writing and erasing are repeated, ions are diffused into the oxide layer 3 only at a location regulated by the ion source diffusion control layer 6, so that the resistance value of the memory element 10 is reduced. It can be stabilized.

In addition, since the ion source diffusion control layer 6 can be configured using a material used for a barrier metal film of a normal semiconductor device, a manufacturing method such as a film forming condition of the ion source diffusion control layer 6 is described in the semiconductor device. The barrier metal film can be formed by the same method.
Furthermore, by using a material having a low resistance value for the ion source diffusion control layer 6, the change in the resistance value of the entire memory element 10 can be made to depend on the change in the resistance value of the oxide layer 3.

  Therefore, the above-described configuration of the memory element 10 can suppress variation in resistance value in a low resistance state when information writing and erasing are repeated, thereby improving the stability and durability of the memory element 10. Can be made.

  Specifically, the memory element 10 of the first embodiment can be manufactured as follows, for example.

  First, a lower electrode 1 made of, for example, W is formed on a substrate on which a CMOS circuit such as a selection transistor is formed. Thereafter, if necessary, oxides on the plug surface are removed by reverse sputtering or the like.

Next, after forming a gadolinium film with a film thickness of, for example, 3 nm on the lower electrode 1 using, for example, a gadolinium target, the gadolinium film is oxidized by oxygen plasma.
Thereby, the oxide layer 3 is formed.

Next, a film having a thickness of 10 nm is formed on the oxide layer 3 using TaN, for example. Thereafter, by using photolithography, the portion other than the portion for forming the opening for contact between the oxide layer 3 and the ion source layer 4 is covered with a mask, and TaN is selectively etched. At this time, for example, the planar shape of the opening is circular and the diameter is 30 nm.
Thereby, the ion source diffusion control layer 6 is formed.

Next, for example, a GeTeGd film is formed on the ion source diffusion control layer 6 and in the opening formed in the ion source diffusion control layer 6 by DC magnetron sputtering.
Thereby, the ion source layer 4 is formed.

Next, for example, a W film is formed on the ion source layer 4 to form the upper electrode 5.
Thereafter, the oxide layer 3, the ion source diffusion control layer 6, the ion source layer 4 and the upper electrode layer 4 are patterned by, for example, plasma etching or the like. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).

  Next, a wiring layer connected to the upper electrode 5 is formed to connect the memory element 10 and a contact for obtaining a common potential.

  In this way, the memory element 10 can be manufactured.

A storage device (memory device) can be configured by arranging a large number of the memory elements 10 having the above-described configuration on a matrix.
FIG. 2 shows a schematic configuration diagram (perspective view) of one embodiment of such a storage device.

In this storage device, for each storage element 10, a plurality of word lines WL connected to the lower electrode 1 side and a plurality of bit lines BL installed on the upper electrode 5 side orthogonal to the word lines WL are provided. The memory element 10 is arranged at each intersection of the word line WL and the bit line BL.
A large number of memory cells 20 formed in this way are arranged to form a memory cell array.
The memory device shown in FIG. 2 shows a memory cell array having a configuration in which 3 × 3 memory cells 20 are arranged in a matrix.

  In such a storage device, by configuring the storage device using the storage element 10 having the above-described configuration, fluctuations in the resistance value during recording and erasing are reduced. For this reason, data deterioration is reduced particularly when the repetitive operation is performed, and information can be read stably. Therefore, a highly reliable storage device that operates stably can be realized.

Further, for example, it is conceivable to form a memory device by forming wirings connected to the upper electrode 5 in common for the entire memory cell array.
3 and 4 are schematic configuration diagrams of one embodiment of the memory cell array configured as described above. 3 is a cross-sectional view, and FIG. 4 is a plan view.

  As shown in FIGS. 3 and 4, in this memory cell array, the memory elements 10 constituting each memory cell are the oxide layer 3, the ion source diffusion control layer 6, the ion source layer 4 and the upper electrode throughout the memory cell. Each layer of 5 is shared. In other words, each storage element 10 includes the same oxide layer 3, ion source diffusion control layer 6, ion source layer 4, and upper electrode 5.

The upper electrode 5 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. A memory element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 3, each storage element 10 constituting each memory cell of the memory cell array is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the memory element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. This metal wiring layer 16 is connected to a bit line BL (see FIG. 4) which is the other address wiring of the memory element.

  In FIG. 4, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 4, reference numeral 21 indicates a contact portion that communicates with the lower electrode 1 of the memory element 10, and 22 indicates a contact portion that communicates with the bit line BL.

The memory cell array shown in FIGS. 3 and 4 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.

Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 5 (plate electrode PL), the resistance value of the memory element 10 transitions to a low resistance state. To do. Thereby, information can be recorded in the memory element 10 of the selected memory cell.
Further, by applying a field voltage, which is a positive potential compared to the potential of the upper electrode 5 (plate electrode PL), to the lower electrode 1, the resistance value of the memory element 10 transitions again to the high resistance state. Thereby, the recorded information can be erased from the storage element 10 of the selected memory cell.

In order to read out recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the memory element 10 is changed. Different currents or voltages are detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the memory element 10 changes.

  According to the memory element 10 of the above-described embodiment, information recording and information reading can be easily performed, and in particular, there is an excellent characteristic that variations in writing and erasing voltage thresholds are small.

  Further, even when the storage device of the above-described embodiment is miniaturized, it is easy to record information and hold recorded information. Therefore, by configuring the storage device using the storage element 10 of the above-described embodiment, the storage device can be integrated (high density) or downsized.

  FIG. 5 shows a schematic configuration diagram (cross-sectional view) of the memory element 30 according to the second embodiment of the present invention.

  The memory element 30 shown in FIG. 5 is, for example, a connection portion with a CMOS circuit portion on a silicon substrate 11 (see FIG. 3) on which a CMOS circuit is formed, similarly to the memory element 10 of the first embodiment. A certain lower electrode 31 is formed, a storage layer 32 is formed on the lower electrode 31, and an upper electrode 35 is formed on the storage layer 32.

  The memory layer 32 is composed of an oxide layer 33 and an ion source layer 34 formed on the oxide layer 33, and an ion source diffusion control layer 36 is formed surrounding the oxide layer 33. Yes.

  The lower electrode 31, the oxide layer 33, and the ion source diffusion control layer 36 are formed in the insulating layer 37. The upper part of the oxide layer 33 and the upper part of the ion source diffusion control layer 36 form substantially the same plane.

For the lower electrode 31, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, WN, TaN, silicide, or the like can be used.
For the upper electrode 35, similarly to the lower electrode 31, a wiring material used in a normal semiconductor process can be used.

The oxide layer 33 is selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y, similarly to the oxide layer 3 of the first embodiment. A material containing two or more kinds of elements (rare earth elements) and oxygen, for example, a rare earth oxide such as gadolinium oxide can be used.
The oxide layer 33 is formed with a film thickness of about 0.5 nm to 10 nm, for example. Thus, by reducing the thickness of the oxide layer 33, it is possible to pass a current through the oxide layer 33 made of a rare earth oxide or the like, which is usually an insulating material.

  The ion source layer 34 contains Cu, Ag, or Zn, and more preferably, further contains a chalcogenide element of Te, Se, S, for example, GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, etc., Cu , Ag, Zn added film, Ag film, Ag alloy film, Cu film, Cu alloy film, Zn film, Zn alloy film, or the like. Moreover, heat resistance can be improved by adding Ge, rare earth elements, etc. to this ion source layer 34 as needed.

The ion source diffusion control layer 36 is not particularly limited as long as it can control the diffusion of Cu, Ag, or Zn ions, but a material having a low resistance value and used in a conventional semiconductor process is preferable. For example, it can be configured using a material used for a barrier metal film of a conventional semiconductor device.
As such a material, for example, a transition metal nitride can be used, and specifically, a nitrogen compound material containing at least one of Ta, Ti, Nb, V, and Zr is used. More specifically, TaN, TaSiN, TiN, NbN, VN, ZrN, or the like can be used.

Further, when the ion source diffusion control layer 36 is formed using the above-described transition metal nitride, the transition metal nitride has conductivity, so that the lower electrode 31 and the ion source diffusion control layer 36 are in contact with each other. If configured, the storage element 30 is short-circuited. For this reason, the ion source diffusion control layer 36 must be formed thinner than the oxide layer 33.
Further, even when a large number of memory elements 30 are arranged to form a memory device as shown in FIGS. 3 and 4, if the ion source diffusion control layers 36 of adjacent memory elements come into contact with each other, the memory elements are short-circuited. Resulting in. For this reason, the insulating layer 37 must be formed between the ion source diffusion control layers 36.
In the case where the ion source diffusion control layer 36 is configured using an insulating material, the above-described structural restrictions on the ion source diffusion control layer 36 are not necessary.

The oxide layer 33 made of the above-described material has a characteristic that the impedance (resistance value) changes when a voltage pulse or a current pulse is applied.
The oxide layer 33 has a sufficiently large change in resistance value than the other layers. Therefore, the change in the resistance value of the entire memory element 30 is mainly influenced by the oxide layer 33. Therefore, information can be recorded in the memory element 30 by using the change in the resistance value of the oxide layer 33.

  Specifically, the memory element 30 of the second embodiment can be manufactured as follows, for example.

  First, a plug-like lower electrode 31 made of W is formed on the insulating layer 37 by, for example, a general plug formation method on a substrate on which a CMOS circuit such as a selection transistor is formed. Thereafter, if necessary, oxides on the plug surface are removed by reverse sputtering or the like.

  Next, by using photolithography, the portion other than the portion where the ion source diffusion control layer 36 is formed is covered with a mask, and the upper portion of the lower electrode 31 and the insulating layer 37 formed in a plug shape is subjected to RIE (reactive ion etching) or the like. Etch. The area of etching at this time is larger than the area of the lower electrode 31.

  Next, after removing the resist, an ion source diffusion control layer 36 is formed by CVD or the like so as to cover the opening by etching. Then, the upper part of the insulating layer 37 and the upper part of the ion source diffusion control layer 36 are flattened by the CMP method so as to be substantially the same plane.

  Next, using photolithography, the portion other than the portion where the oxide layer 33 is formed is covered with a mask, and the ion source diffusion control layer 36 is etched by RIE or the like. The etching area at this time is set to an area equal to or smaller than the area of the lower electrode 31. The etching depth is set to a position deeper than the ion source diffusion control layer 36.

  Next, after removing the resist, an oxide layer 33 is formed by CVD or the like so as to cover the opening by etching. Then, the upper part of the insulating layer 37, the upper part of the ion source diffusion control layer 36, and the upper part of the oxide layer 33 are planarized by the CMP method so as to be substantially the same plane.

Next, a GeTeGd film, for example, is formed on the oxide layer 33, the ion source diffusion control layer 36, and the insulating layer 37 by DC magnetron sputtering.
Thereby, the ion source layer 34 is formed.

Next, for example, a W film is formed on the ion source layer 34 to form the upper electrode 35.
Thereafter, the ion source layer 34 and the upper electrode layer 35 are patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE.

  Next, a wiring layer connected to the upper electrode 35 is formed to connect the memory element 30 and a contact for obtaining a common potential.

  In this way, the memory element 30 can be manufactured.

The memory element 30 configured as described above configures the memory device (memory device) illustrated in FIG. 2 by arranging a large number of memory elements 30 on a matrix, similarly to the memory element 10 of the first embodiment. be able to.
For example, the memory device shown in FIGS. 3 and 4 can be configured by forming wirings connected to the upper electrode 35 in common in the entire memory cell array.

  The memory element 30 having the above-described configuration can store information by operating in the same manner as the memory element 10. Similarly, information can be stored in a storage device using the storage element 30.

The memory element 30 having the above-described configuration has the same function and effect as the memory element 10 of the first embodiment.
Further, for example, when the memory element 30 is reduced in size, the oxide layer 33 becomes sufficiently small, and the connection portion with the ion source layer 34 need not be regulated by the ion source diffusion control layer 36. The diffusion of ions from the ion source layer 34 to the insulating layer 37 can be regulated. For this reason, it is possible to prevent a decrease in resistance value at the time of erasing the memory element due to ion diffusion into the insulating layer 37.
Therefore, it becomes easy to record information when the storage element 30 is downsized and to hold the recorded information, and the storage device can be integrated (high density) and downsized.

(Example)
Next, the memory element 10 described above was actually fabricated and its characteristics were evaluated.
In an actual memory device, as shown in FIGS. 2 to 4, memory elements are arranged in an array, or there are circuit elements such as transistors in addition to the memory element portion.
The characteristic evaluation test device (characteristic evaluation element) shown in Fig. 1 was prepared, and the characteristics were measured and evaluated.
FIG. 6A is a plan view of the manufactured test device, and FIG. 6B is a cross-sectional view taken along the line AA ′ of the test device of FIG. 6A. With this test device, the characteristics of the memory element were measured and evaluated.

In this characteristic evaluation test device, a lower electrode 1 common to the memory element 10 of each memory cell is formed on a silicon substrate. Then, the oxide layer 3 of the memory element 10, the ion source diffusion control layer 6 having an opening, and the ion source layer 4 are formed.
The lower electrode 1 is processed into a plug shape so that the upper part becomes a convex part in a pattern smaller than the lower part in accordance with the memory cell, and the opening of the ion source diffusion control layer 6 is the convex part of the lower electrode 1. It is arranged above.

The oxide layer 3 and the ion source diffusion control layer 6 are formed in the vertically long element formation region 43 shown in FIG. 6A. The ion source layer 4 is connected to the oxide layer 3 through the opening of the ion source diffusion control layer 6.
Connection terminal pads 44 for the lower electrode 1 are formed on the left and right sides of the element formation region 43, and connection terminal pads 45 for the upper electrode 5 are formed on both ends of the upper electrode 5.

  Specifically, the test device for characteristic evaluation shown in FIGS. 6A and 6B was produced as follows.

First, 100 nm of WN was deposited as a material for the lower electrode 1 on a Si substrate having a thickness of 2 mm.
Thereafter, the lower electrode 1 connected to the element portion and the measurement lower electrode terminal pad 24 are masked using photolithography, and WN is etched by 50 nm to form the plug-like lower electrode 1. At that time, the shape of the portion of the lower electrode 1 connected to the element portion (that is, the convex portion described above) was circular, and its diameter was 340 nm.

Next, 50 nm of SiO ₂ was deposited as the insulating layer 42, and the resist was peeled off by a known lift-off method to form the upper portion of the plug-like lower electrode 1 and the insulating layer 42 on a substantially flat surface.

  Further, gadolinium oxide, which is a rare-earth oxide film having a thickness of 3 nm, was formed as the oxide layer 3 on the lower electrode 1 of the element portion. Further, TaN having a film thickness of 10 nm, which is a nitrogen compound of a transition metal, is formed as an ion source diffusion control layer 6 on the oxide layer 3, and the oxide layer 3 and the ion source diffusion control layer 6 are stacked. A film was formed.

Next, after masking a range of 200 μm wide × 600 μm long as an element formation region using photolithography, the laminated film composed of the oxide layer 3 and the ion source diffusion control layer 6 is subjected to Ar plasma, The laminated film was etched.
Thereafter, by using photolithography, TaN in the ion source diffusion control layer 6 was selectively etched by covering other than the openings formed in the ion source diffusion control layer 6 with a mask.
Thus, an opening of the ion source diffusion control layer 6 where the oxide layer 3 and the ion source layer 4 contact each other was formed. At this time, the opening of the ion source diffusion control layer 6 had a circular planar shape and a diameter of 30 nm.

Furthermore, after masking portions other than the upper electrode 5, the connection terminal pad 44 of the lower electrode 1 and the connection terminal pad 45 of the upper electrode 5 using photolithography, the film thickness of 20 nm becomes the ion source layer 4 A laminated film of a CuGeTeGd film and a 12 nm-thickness Cu film was formed. Further, a laminated film of a Cr film with a thickness of 20 nm, a Cu film with a thickness of 100 nm, and an Au film with a thickness of 100 nm was formed to serve as the connection terminal pad 44 of the lower electrode 1 and the connection terminal pad 45 of the upper electrode 5. .
Thereafter, the mask was removed by a known lift-off method to form the ion source layer 4, the upper electrode 5, the lower electrode connecting terminal pad 44, and the upper electrode connecting terminal pad 45.

  As described above, a semiconductor memory element characteristic evaluation test device was manufactured by a known etching and lithography technique.

(Comparative example)
Next, as a comparative example, a test device was manufactured in the same manner as in the example except that an insulating layer was formed using SiO ₂ instead of forming the ion source diffusion control layer 6 using TaN.

(Characteristic evaluation)
Continuous operation of writing and erasing information by continuously applying positive and negative pulses of 2.5 V, 100 ns to both ends of the storage element terminal with respect to the test device for characteristic evaluation manufactured in Examples and Comparative Examples Went. Then, the resistance value in the writing state and the resistance value in the erasing state of the test device were measured. It should be noted that the number of times of pulse application during the continuous operation is 1 × 10 ⁸ times.

FIG. 7 shows the resistance values of the test devices manufactured in the examples with respect to the resistance value in the written state and the resistance value in the erased state thus obtained. Moreover, the resistance value of the test device produced by the comparative example is shown in FIG.
7 and 8, the vertical axis represents the resistance value (Ω), and the horizontal axis represents the number of operations (times). Also, the upper point in the figure is the resistance value in the erased state, and the lower point is the resistance value in the written state.

According to FIG. 7, in the test device manufactured in the example, the resistance value in the writing state and the resistance value in the erasing state are both the first resistance after the continuous operation of writing and erasing is performed 1 × 10 ⁸ times. The value is almost the same as the value.
On the other hand, in the comparative example shown in FIG. 8, when the continuous operation of writing and erasing is performed, the resistance value in the erasing state is lowered and the variation of the resistance value is large as the number of operations increases. This is because when the operation is repeated, Cu ions in the ion source layer 4 are diffused into the oxide layer 3, thereby reducing the resistance value of the oxide layer 3 and reducing the resistance value of the entire test device. Conceivable.

  Therefore, by providing the ion source diffusion control layer 6 between the oxide layer 3 and the ion source layer 4 and restricting the connection area between the oxide layer 3 and the ion source layer 4, the Cu in the ion source layer 4 can be controlled. It can be seen that ions can be prevented from diffusing into the oxide layer 3. Even when information writing and erasing are repeated, the resistance value of the memory element, particularly the resistance value in the erased state does not decrease, so that the stability and durability of the memory element can be improved.

  A memory device (memory device) can be formed by arranging a large number of memory elements, for example, in a column shape or a matrix shape, using the memory element of the present invention described above. In addition, a memory cell can be configured by connecting a MOS transistor or a diode for selecting an element to each memory element as necessary. Furthermore, it can be connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, and the like via wiring.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. Any memory form such as a memory) can be applied.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of a memory element according to a first embodiment of the present invention. It is a schematic block diagram (perspective view) of the memory | storage device using the memory element of FIG. It is a schematic block diagram (sectional drawing) of the memory cell array using the memory element of FIG. FIG. 2 is a schematic configuration diagram (plan view) of a memory cell array using the memory element of FIG. 1. It is a schematic block diagram (sectional drawing) of the memory element of the 2nd Embodiment of this invention. It is a schematic block diagram (plan view) of a test device for A characteristic evaluation. It is a schematic block diagram (sectional drawing) of the test device for B characteristic evaluation. It is a figure which shows the repetition characteristic of the read-out resistance value of an Example. It is a figure which shows the repetition characteristic of the read-out resistance value of a comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,31 Lower electrode, 2,32 Memory layer, 3,33 Oxide layer, 4,34 Ion source layer, 5,35 Upper electrode, 6,36 Ion source diffusion control layer, 10 Memory element, 11 Semiconductor substrate, 12 Element isolation layer, 13 source / drain region, 14 gate electrode, 15 plug layer, 16 metal wiring layer, 17 plug layer, 18 active region, 20 memory cell, 30 memory element, 37 insulating layer, 43 element formation region, 44 bottom Electrode connection terminal pad, 45 Upper electrode connection terminal pad, BL bit line, PL plate electrode, Tr MOS transistor, WL Word line

Claims (6)

A storage layer is disposed between the first electrode and the second electrode,
The storage layer includes an oxide layer made of an oxide of a rare earth element and an ion source layer containing at least one selected from Cu, Ag, or Zn to be ionized,
One or more elements selected from Ta, Ti, Nb, V, and Zr are in contact with the oxide layer and the ion source layer and around a connection portion between the oxide layer and the ion source layer . a nitride, that the ion source diffusion control layer for regulating the diffusion of ions provided
Serial憶素Ko. The ion source diffusion control layer is stacked between the oxide layer and the ion source layer, and the oxide layer and the ion source layer are connected through an opening formed in the ion source diffusion control layer. memory element according to 請 Motomeko 1 that is. The ion source layer, the memory device according to 請 Motomeko 1 you containing a rare earth element. Wherein the storage layer by applying a voltage pulse or a current pulse, said impedance of the storage layer is changed, the memory device according to 請 Motomeko 1 recorded Ru done information. A memory layer is disposed between the first electrode and the second electrode, and the memory layer is at least one selected from an oxide layer made of an oxide of a rare earth element and ionizing Cu, Ag, or Zn. An ion source layer containing a kind, in contact with the oxide layer and the ion source layer, and around a connection portion between the oxide layer and the ion source layer, Ta, Ti, A storage element provided with an ion source diffusion control layer for restricting ion diffusion, comprising a nitride of one or more elements selected from Nb, V, and Zr ;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
That Do is arranged a number said storage element
Storage peripherals. In the adjacent plurality of memory elements, storage device according to claim 5 at least some of the layers constituting the memory element that is formed commonly by the same layer.

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