JP4872526B2 - Storage device - Google Patents

Description

  The present invention relates to a memory device including a memory element in which a resistance value of a memory layer changes by applying potentials having different polarities to two electrodes, and is suitable for application to a nonvolatile memory.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

  However, in the memory element having a structure in which Cu, Ag, or Zn is contained in either the upper electrode or the lower electrode and GeS or GeSe amorphous chalcogenide material is sandwiched between the electrodes, the above-described ion conduction that causes a change in resistance. Crystallization is promoted due to temperature rise during the manufacturing process, temperature rise due to Joule heat of the recording current, long-term heat load during data storage, and full or partial crystallization As a result, the original electrical characteristics such as a change in the resistance value of the memory element and a change in the recording / erasing operation voltage are changed.

Therefore, the present applicant firstly uses a thin film of various oxides for the memory layer on which information is recorded by changing the resistance to form a relatively high resistance memory layer and is in contact with the memory layer. A memory element in which a layer containing Cu, Ag, Zn is arranged has been proposed (see Patent Document 2).
By using an oxide thin film for the memory layer, this memory layer serves as a barrier for electrical conduction.

In this memory element, an element selected from Te, S, and Se (chalcogen element) can be contained in the layer containing Cu, Ag, and Zn. By including the chalcogen element in this manner, the metal element of Cu, Ag, Zn and the chalcogen element are combined to form a metal chalcogenide layer.
This metal chalcogenide layer mainly has an amorphous structure and serves as an ion conductor.

In this memory element, when a positive potential is applied to one electrode on the layer side containing Cu, Ag, and Zn, Cu, Ag, and Zn are ionized and diffused into the memory layer (oxide thin film). The resistance value of the memory layer is lowered and the resistance value of the memory element is also lowered by being deposited in combination with electrons near the other electrode or by staying in the memory layer and forming an impurity level of the insulating layer. . Thereby, information is written.
On the other hand, when a negative potential is applied to one electrode on the layer side containing Cu, Ag, Zn from this state, Cu, Ag, Zn deposited on the other electrode side is ionized again, and one electrode side By returning to this layer, the resistance value of the memory layer returns to the original high state, and the resistance value of the memory element also increases. Thereby, the written information is erased.
For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information is written from “0” to “0” in the process of writing information by applying a positive voltage. Instead of “1”, it can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  In this memory element, by using an oxide in the memory layer, recorded information can be stably held even in a high temperature environment or during long-term storage, and the above-described problems can be solved. become.

Special Table 2002-536840 Publication JP 2005-197634 A Nikkei Electronics January 20, 2003 issue (page 104)

  However, in a memory element using an oxide thin film as the memory layer, the resistance value after the erasing process for changing the memory element from the low resistance state to the high resistance state may vary.

If the resistance value after the erasing process varies, when the recorded information is read out, it cannot be read out accurately and a read error may occur.
Therefore, it is desired to eliminate such variation in resistance value after the erasing process.

  In order to solve the above-described problems, in the present invention, it is possible to suppress the occurrence of variations in the resistance values of the memory elements that constitute the memory cell, and to stably perform the information recording operation and the recorded information reading. A storage device that can be used is provided.

In the memory device of the present invention, a memory layer made of an amorphous rare earth element oxide is disposed between two electrodes, and any one metal selected from Cu, Ag, and Zn is in contact with the memory layer. A storage element including a layer including an element and a conductive path containing a metal element (Cu, Ag, Zn) in a local region in the storage layer of the storage element by applying a voltage between the two electrodes And the amount of current flowing through the memory element is controlled so that the crystallographic structure of the conduction path is not crystallized and is kept amorphous .

According to the configuration of the memory device of the present invention described above, a memory layer made of an amorphous rare earth oxide is disposed between two electrodes, and Cu, Ag, and Zn are in contact with the memory layer. By including a memory element provided with a layer containing any of the selected metal elements, information can be recorded in the memory element due to a change in the resistance value of the memory layer.
Also, by applying a voltage between the two electrodes, a conduction path containing a metal element (Cu, Ag, Zn) is formed in a local region in the memory layer of the memory element. In addition, the metal element-containing layer and the electrode on the memory layer side are conducted through the conduction path, and the resistance value of the memory layer is changed from the high resistance state to the low resistance state by the conduction path.
When the memory layer is in a low resistance state and a voltage having a polarity opposite to that for forming the conduction path between the two electrodes is applied, the metal element of the conduction path is changed to the original layer (the metal element Therefore, the conduction path is eliminated, the conduction between the layer containing the metal element and the electrode on the memory layer side is cut off, and the resistance value of the memory layer is changed from the low resistance state to the high resistance state.
Further, when the crystalline structure of the conduction path is amorphous, most of the metal elements in the conduction path exist in the state of metal ions in the memory layer, so that a conduction path is formed between the two electrodes. When applying a voltage of the opposite polarity to canceling the conduction path, it is easy to move the metal element due to the effect of Coulomb force, and the metal element remains in the memory layer in a high resistance state. It becomes possible to suppress. Thereby, it is possible to suppress variations in resistance value after the process of changing the memory layer from the low resistance state to the high resistance state (the erasing process described above).

According to the above-described present invention, it is possible to suppress variation in resistance value after the process of changing the memory layer from the low resistance state to the high resistance state (erasing process). Information can be read stably.
Therefore, according to the present invention, a highly reliable storage device with stable operation can be realized.

  First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.

The present inventors have used a transmission electron microscope (TEM) and an energy dispersive X-ray spectrometer (EDX) attached to the TEM to clarify the cause of the resistance variation after the erasing process. The crystal structure and the composition distribution structure of the memory element constituting the structure were analyzed.
As a result of the analysis, it was found that the factor that determines the variation in resistance value after the erasing process is the crystallographic structure of the conduction path formed in the memory layer in the writing process.

Therefore, the present invention has a structure in which a conduction path containing Cu, Ag, and Zn is formed in the memory layer in the writing process, and the crystallographic structure of the conduction path is amorphous.
Since the conduction path is amorphous, it is possible to suppress variation in resistance value after the erasing process.

On the other hand, if the conduction path is crystalline, the resistance value after the erasing process tends to vary.
This is presumably because Cu, Ag, and Zn that formed the conduction path remain in the memory layer even after the erasing process.
In the writing process, Cu, Ag, and Zn are ionized and then diffused by the heat generated by the current and the Coulomb force. In the writing process, if the amount of current is large or the temperature is high, the reduction reaction of the metal ions is promoted and the crystallization is facilitated. In the erasing process, the metal element escapes from the memory layer and returns to its original state due to the effect of the heat generated by the Coulomb force and current, but when the conduction path crystallizes and has the properties of a metal-bonding material, ionization occurs. More energy is required, and the effect of the Coulomb force becomes relatively small.

  Therefore, it is desirable to control the amount of current flowing through the memory element and the temperature of the memory element (particularly the temperature of the memory layer) so that the conduction path is not crystallized in the writing process.

  Subsequently, specific embodiments of the present invention will be described.

FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a memory element that constitutes a memory device according to an embodiment of the present invention.
This memory element is configured by arranging a large number of variable resistance elements 10 constituting a memory cell in an array.

The resistance change element 10 includes a memory layer 2 in which information is recorded by changing a resistance state between the lower electrode 1 and the upper electrode 4, and one or more elements selected from Cu, Ag, and Zn. And the layer 3 to be sandwiched.
One or more elements selected from Cu, Ag, and Zn are ionized to change the resistance value of the memory layer 2 as described above, and thus serve as an ion source.
Hereinafter, a layer containing one or more elements (ion source elements) selected from Cu, Ag, and Zn is referred to as an ion source layer 3.

The ion source layer 3 contains one or more elements (chalcogenide elements) selected from S, Se, and Te in addition to one or more elements (ion source elements) selected from Cu, Ag, and Zn. You may let them.
Specifically, for example, a CuTeGeGd film or a CuTeGe film can be used as the ion source layer 3 described above.

For the memory layer 2, an oxide of a rare earth element is used.
By using a rare earth element oxide for the memory layer 2, the melting point of the rare earth element oxide is high, so that the stability of the memory layer 2 in a high temperature environment can be increased.

  Arbitrary rare earth elements can be used as the rare earth elements used in the memory layer 2, but preferably one or more rare earth elements selected from Y, La, Nd, Sm, Gd, Tb, and Dy are used. .

In the configuration of FIG. 1, each resistance change element 10 is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the resistance change element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. The metal wiring layer 16 is connected to a bit line BL (see FIG. 2) which is the other address wiring of the memory element.

  Further, the variable resistance element 10 constituting each memory cell shares the layers of the memory layer 2, the ion source layer 3, and the upper electrode 4 throughout the memory cell array portion (memory portion). In other words, each resistance change element 10 is composed of the same memory layer 2, ion source layer 3, and upper electrode 4.

The upper electrode 4 formed in common serves as a plate electrode PL described later.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. The resistance change element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

FIG. 2 shows a schematic plan view of the memory element of this embodiment.
In FIG. 2, the active region 18 of the MOS transistor Tr is indicated by a chain line. In the figure, reference numeral 21 denotes a contact portion that leads to the lower electrode 1 of the variable resistance element 10, and 22 denotes a contact portion that leads to the bit line BL.

  As shown in FIG. 2, the plate electrode PL is formed over the entire memory cell array portion (memory portion).

Next, a method for manufacturing the memory element having the configuration shown in FIGS. 1 and 2 will be described.
This memory element can be manufactured, for example, as follows.

First, the MOS transistor Tr is formed on the semiconductor substrate 11.
Thereafter, an insulating layer is formed covering the surface.
Next, a via hole is formed in this insulating layer.
Subsequently, the inside of the via hole is filled with an electrode material such as W, WN, or TiW by a method such as CVD or plating.
Next, the surface is planarized by a CMP method or the like.
By repeating these steps, the plug layer 15, the metal wiring layer 16, the plug layer 17, and the lower electrode 1 can be formed, and the lower electrode 1 can be patterned for each memory cell.

Subsequently, a memory layer 2 made of a rare earth element oxide is deposited on the entire surface of the lower electrode 1 formed separately for each memory cell.
At this time, it is desirable that the surface of the lower electrode 1 is ideally formed at the same height as the surrounding insulating layer and is flattened.
For example, a gadolinium oxide film is deposited as the memory layer 2. This gadolinium oxide film can be formed by performing thermal oxidation or plasma oxidation in an oxygen-containing plasma atmosphere after depositing a metal gadolinium film. The crystallographic structure of this gadolinium oxide film is amorphous.

  Next, an ion source layer 3 is entirely deposited on the storage layer 2. For example, a CuTeGeGd film having a thickness of 20 nm is deposited as the ion source layer 3. Since CuTeGeGd is a material having a low resistance, it can be used as the upper electrode 4 as it is. However, it is desirable to use a material having a lower resistance for the upper electrode 4.

  Further, the upper electrode 4 is deposited on the entire surface of the ion source layer 3. For example, as the upper electrode 4, a metal material having a lower resistance than the material of the ion source layer 3, a low-resistance nitride such as silicide, TaN, or Wn is deposited.

Thereafter, the memory layer 2, the ion source layer 3, and the upper electrode 4 formed over the entire surface are patterned so as to remain over the entire memory cell array portion (memory portion).
At this time, since the pattern is processed over the entire memory cell array portion (memory portion), it is not necessary to use the most advanced ultra-fine processing technology.
Note that heat treatment is performed after all the steps, whereby the memory element can have a structure with high thermal stability.

  In the present embodiment, particularly in a writing process (a process of transitioning from a high resistance state to a low resistance state), an enlarged view of the main part of the memory element in FIG. A conductive path 31 containing an ion source element (Cu, Ag, Zn) is formed by connecting the lower electrode 1 and the ion source layer 3, and the crystallographic structure of the conductive path 31 is amorphous. It has a certain configuration.

  Since the crystallographic structure of the conductive path 31 is amorphous, the variation in resistance value after the erasing process (the process of transitioning from the low resistance state to the high resistance state) is reduced, as will be described in detail later. Can do.

  As described above in the outline of the present invention, the crystallographic structure of the conduction path 31 depends on the amount of current and the temperature in the writing process for forming the conduction path 31, so that the conduction path 31 is not crystallized. The writing process is performed by controlling the amount of current flowing through the resistance change element 10 and the temperature of the memory layer 2.

Next, the operation of the memory element in the memory device of this embodiment will be described.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain 13 of the MOS transistor Tr. Applied.

  Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 4 (plate electrode PL), the metal serving as the ion source contained in the ion source layer 3 The element (Cu, Ag, Zn) moves in the direction of the lower electrode 1 as ions. When these ions are implanted into the memory layer 2 and diffused or precipitated, the electrical properties of the memory layer 2 are locally changed, and the conduction path 31 shown in FIG. 3 is formed in the memory layer 2. Therefore, the resistance value of the memory layer 2 becomes a low resistance state, and the resistance value of the resistance change element 10 also changes to the low resistance state. Thereby, information can be written in the resistance change element 10 of the selected memory cell.

  Further, by applying a voltage having a positive potential relative to the potential of the upper electrode 4 (plate electrode PL) to the lower electrode 1, the metal element of the conduction path 31 in the memory layer 2 becomes ions, and the upper electrode 4 By moving in the direction of the electrode 4 (plate electrode PL), the conduction path 31 in the memory layer 2 is eliminated, so that the resistance value of the memory layer 2 becomes a high resistance state and the resistance value of the resistance change element 10 is also high. Transition to the resistance state. Thereby, the written information can be erased from the variable resistance element 10 of the selected memory cell.

Then, after the erasing process for transition from the low resistance state to the high resistance state, the conduction path 31 is eliminated as described above.
However, if the crystallographic structure of the conduction path 31 is crystalline, the energy required to ionize the metal element in the metal-bonded state becomes large, and therefore the conduction path 31 in the memory layer 2 even after the erasing process. This metal element may remain, and the resistance value of the memory layer 2 may be lowered by the remaining metal element. Such a phenomenon is considered to cause variations in resistance values after the erasing process.
On the other hand, when the crystallographic structure of the conduction path 31 is amorphous, most of the metal elements in the conduction path 31 are present in the state of metal ions in the memory layer 2, so the effect of the Coulomb force. It is easy to move the metal element due to, and it is possible to prevent the metal element from remaining in the memory layer 2 during the erasing process. Thereby, it is considered that variation in resistance value after the erasing process can be suppressed.

In order to read the recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the resistance change element 10 is determined. Thus, a different current or voltage is detected through a sense amplifier (not shown) connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the resistance change element 10 changes.

In addition, by making the film thickness of the memory layer 2 very thin, for example, about several nm, it becomes possible to suppress interference between adjacent memory cells.
Further, the memory layer 2 needs to have a difference in resistance value at least so that a read signal can be sufficiently secured between the high resistance state and the low resistance state. For example, a difference of 30% or more is necessary.

According to the above-described embodiment, the ion source element is formed by connecting the lower electrode 1 and the ion source layer 3 in the memory layer 2 in the writing process in which the memory layer 2 is transitioned from the high resistance state to the low resistance state. A conduction path 31 containing (Cu, Ag, Zn) is formed, and the crystallographic structure of the conduction path 31 is controlled to be amorphous.
Accordingly, when the ion source element is ionized and returned to the ion source layer 3 to eliminate the conduction path 31 in the erasing process in which the memory layer 2 is transitioned from the low resistance state to the high resistance state, the ion source element is easily changed. It can be ionized and moved to the ion source layer 3. For this reason, it is possible to suppress the ion source element from remaining in the memory layer 2 after the erasing process, and to suppress variations in the memory layer 2 after the erasing process.

As described above, it is possible to suppress the variation in the resistance value of the memory layer 2 after the erasing process, so that it is possible to read the recorded information accurately without generating a read error. In addition, it is possible to avoid an erase failure in which the resistance value of the memory layer 2 after the erase process remains in a low resistance state.
As a result, the operation of recording information and the reading of recorded information can be performed stably.
Therefore, a highly reliable storage device with stable operation can be realized.

  In the above-described embodiment, the memory cell array is configured by forming each layer such as the memory layer 2 in common in a certain number of memory cells. However, the range of the memory cell in which each layer is formed in common is not particularly limited. Various configurations are possible, such as only memory cells in the same row or column, memory cells in two rows or two columns, and 4 × 2 vertical and horizontal memory cells.

In the above-described embodiment, the memory layer 2, the ion source layer 3, and the upper electrode 4 are formed in common in adjacent memory cells, but each layer may be formed individually by patterning for each memory cell.
In addition, the range of layers formed in common in adjacent memory cells may be changed from that in the above embodiment, and only the memory layer or the memory layer and the ion source layer may be formed in common.
Further, the storage layer may be formed on the ion source layer by reversing the stacking order of the storage layer and the ion source layer.
Furthermore, in the present invention, the film structure of the memory element is not limited to the film structure described in the above embodiment, and other film structures are possible.

(Example)
Here, a memory element actually constituting the memory device was manufactured, and characteristics, an internal structure, and the like were examined.

  Each layer of the resistance change element 10 includes a lower electrode 1 as WN, a memory layer 2 as a 2 nm thick gadolinium oxide layer (Gd-O layer), an ion source layer 3 as a 20 nm thick CuTeGe film, and the upper electrode 4 as a WN. , And the memory element shown in FIG. 1 was produced.

Then, two types of samples having different gate sizes of the MOS transistor Tr were produced. Specifically, the size of the gate between the source region and the drain region can be changed by changing the gate electrode 14 of the MOS transistor Tr.
In sample 1, the gate size of the MOS transistor Tr was 0.36 μm × 0.18 μm.
In sample 2, the size of the gate of the MOS transistor Tr was 2.5 μm × 0.18 μm.

For each sample prepared, a writing process was performed by applying a pulse voltage of −2 V to the lower electrode 1 of the memory element for 1 μsec, and an erasing process was performed by applying a pulse voltage of +2 V to the lower electrode 1 for 1 μsec. .
The current flowing through the memory cell is limited by the size of the gate of the MOS transistor Tr, and was 250 μA in sample 1 and 2 mA in sample 2.

The Gd—O layer of the storage layer 2 serves as a barrier for electrical conduction, and the ion source layer 3 serves as an ion conductor.
Although the resistance value of the resistance change element 10 of the memory cell in the unrecorded state is determined by the resistance of the Gd-O layer, it was 500 kΩ in each sample.

(Observation of EDX mapping image)
In each sample, samples for TEM and EDX analysis in each of the initial state, the written state (the state after the writing process), and the erased state (the state after the erasing process) were collected. Specifically, a cross section in the stacking direction of each layer 2, 3, 4 of the resistance change element 10 was thinned by FIB (focused Ga ion beam etching) to prepare a sample.
The prepared sample was subjected to EDX analysis to obtain an EDX mapping image. In the EDX analysis, an EDX spectrum at each point was acquired while scanning an electron beam collected to a diameter of about 1 nm on the cross section of the sample at 1 nm intervals. Then, the integrated intensity of the EDX peaks of Cu-Kα1, Gd-Lα1, and Te-Lα1 is expressed in gray scale contrast, and the surface distribution is plotted, thereby obtaining a mapping image of each element of Cu, Gd, and Te. . However, since the gray scale indicating the peak intensity is not quantified, the element mapping image of EDX shows a qualitative element distribution state.

In the sample 1, EDX mapping images of cross sections in the initial state, the write state, and the erase state are shown in FIGS. 4, 5, and 6, respectively.
FIGS. 7 and 8 show EDX mapping images of cross sections of the sample 2 in the written state and the erased state, respectively.
4 to 8, schematic diagrams illustrating the composition distribution structure are shown on the left side of each figure, and mapping images of Cu, Gd, and Te elements are shown side by side on the right side of each figure.

  From the EDX mapping image in the initial state of Sample 1 shown in FIG. 4, it can be seen that it has a stacked structure of a Gd—O layer and a CuTeGe layer. Note that the Gd element contained in the CuTeGeGd film at the time of film formation is taken into the Gd—O layer after the film formation by a strong bonding force with the O element.

From the mapping image of the writing state of Sample 1 shown in FIG. 5, in the writing state, a Cu composition-rich conduction path is observed in the local region in the Gd-O layer and a Cu composition-rich precipitation phase is observed on the lower electrode side. .
The diameter of this conduction path is estimated to be about 5 nm. In the conduction path, the Cu element remains in the Gd—O layer, and it is considered that the resistance value is lowered by forming the impurity level of the insulating film or by having metal conductivity.
The Cu ions in the metal chalcogenide (CuTeGe) layer diffuse and invade into the local region of the Gd-O layer to form a conduction path, and the effect of the Coulomb force that the Cu ions receive from the electric field and the Joule heat The effect of thermal diffusion due to can be considered.

Here, an electron diffraction pattern (nano-area diffraction) was obtained by irradiating the electron beam focused on the portion of the conduction path (with a diameter of about 1 nm) onto the sample 1 in the written state. The obtained electron diffraction pattern is shown in FIG. 9A.
From FIG. 9A, in the obtained electron diffraction pattern, the position of the diffraction peak is not clear, and an halo-shaped pattern having a broad peak intensity distribution (hereinafter referred to as a halo-pattern) is observed.
This result shows that the crystallographic structure of the conduction path is amorphous.

Further, the element density of each element of Gd and O was measured for the Gd—O layer of the memory layer 2 by a high-resolution Rutherford back-scattering spectroscopy (HRBS).
The measurement results are shown in Table 1 in comparison with the value of crystal Gd ₂ O ₃ .

From Table 1, it can be seen that the Gd—O layer of the memory layer 2 has a structure with many gaps that is 20 to 30% lower in density than the crystal Gd ₂ O ₃ (standard sample).

From the electron diffraction results (FIG. 9A) and the HRBS results (Table 1), it is considered that the conduction path in FIG. 5 has a structure in which Cu element diffuses and penetrates into the gaps of the amorphous Gd—O layer.
Since the Gd-O layer is an oxide with strong ion bonding properties, most of the Cu diffused and penetrated into the Gd-O layer is considered to exist as Cu ions.

  From the mapping image of the erased state of Sample 1 shown in FIG. 6, in the erased state, a precipitated phase rich in Cu composition is observed on the lower electrode side. In addition, a small amount of Cu is observed in the Gd-O layer adjacent to the precipitated phase, but the conduction path that is rich in Cu composition that connects the precipitated phase and the CuTeGe layer in FIG. Has been.

The following phenomenon is considered to occur as a mechanism in which the conduction path is eliminated and the conduction is cut off.
By applying a negative potential to the upper electrode side in contact with the CuTeGe layer, Cu in the conduction path moves and diffuses into the CuTeGe layer due to a synergistic effect of the thermal diffusion effect due to Joule heat and the Coulomb force received from the electric field. Start. The current stops when the Cu composition in the conduction path decreases, the conduction path is eliminated, and the conduction is interrupted. When the current stops flowing, the effect of thermal diffusion due to Joule heat is lost, so Cu loses a driving force sufficient to move and diffuse, and maintains a state where conduction is cut off.
When the conduction is interrupted, the resistance of the Gd-O layer returns to the original high state, and the resistance of the resistance change element 10 also increases, so that the written information can be erased.
The resistance value of the resistance change element 10 after erasing was approximately equal to that in the unrecorded state, and was about 500 kΩ.

From the mapping image of the writing state of Sample 2 shown in FIG. 7, in the writing state, a Cu composition-rich conduction path is observed in the local region in the Gd-O layer, and a Cu composition-rich precipitation phase is observed on the lower electrode side. . This is the same as the writing state of Sample 1 shown in FIG.
Further, the diameter of the conduction path is estimated to be about 10 nm, which is larger than the conduction path of Sample 1.

Here, the electron diffraction pattern was obtained by irradiating the sample in the written state of Sample 2 with an electron beam converged on the conduction path (about 1 nm in diameter). The obtained electron diffraction pattern is shown in FIG. 9B.
FIG. 9B shows that a spot-like diffraction peak is observed in the obtained electron diffraction pattern, and the crystallographic structure of the conduction path is crystalline.
The electron diffraction pattern includes a fcc (111) diffraction peak having a surface spacing of 0.2 nm and a fcc (220) diffraction peak of 0.12 nm. This result suggests that metal Cu having an fcc (face centered cubic lattice) structure was deposited in the conduction path.

  The cause of the crystallization of the conduction path of sample 2 is that the current value at the time of writing is larger than that of sample 1, and the effect of increasing the Cu concentration in the conduction path or the crystallization due to Joule heat. An effect etc. can be considered.

From the mapping image of the erased state of Sample 2 shown in FIG. 8, in the erased state, a precipitated phase rich in Cu composition is observed on the lower electrode side. Further, the remaining Cu composition is observed in the Gd—O layer adjacent to the precipitated phase, and the remaining amount is larger than that of the sample 1. As a result, the Cu composition-rich conduction path connecting the precipitated phase and the CuTeGe layer in FIG. 7 is not sufficiently eliminated, causing a low resistance.
The mapping image in the initial state of sample 2 is substantially the same as the mapping image in the initial state of sample 1, although not shown.

(Resistance variation)
In the memory elements of Sample 1 and Sample 2, writing and erasing were performed on 4000 memory cells, respectively, and the resistance values in the initial state, the writing state, and the erasing state of each memory cell were measured.
As a measurement result, the integrated distribution of resistance values in each state is plotted and shown in FIGS. 10A and 10B. FIG. 10A shows the integrated distribution of resistance values of Sample 1, and FIG. 10B shows the integrated distribution of resistance values of Sample 2. In the integrated distribution, the percentage of the number of cells having a specific resistance value (R) or less is 4000%.

10A and 10B, variations in resistance values in the erased state are compared.
In the sample 1 shown in FIG. 10A, the value of the resistance in the initial state is about 90% or more (about 500 kΩ). The remaining 10% of cells have a resistance value of 50 kΩ to 500 kΩ, but a difference of one or more digits in resistance value is ensured from the resistance value in the written state (5 kΩ).
That is, it can be seen that in Sample 1, the variation in the resistance value in the erased state is sufficiently small.
On the other hand, in the sample 2 shown in FIG. 10B, the resistance value in the erased state is distributed over a wide range of 2 kΩ to 500 kΩ, and the variation is large. There are about several tens of percent of memory cells that are difficult to distinguish from the resistance value in the written state (about 1 kΩ). Further, there are memory cells that have not returned to the high resistance state and cannot be erased.

Here, the reason why the variation in resistance value in the erased state of sample 2 is larger than that of sample 1 will be considered.
In Sample 2, since the metal Cu in the conduction path is crystalline, the Coulomb force received when the erase voltage is applied is smaller than that of the Cu ion, so that the movement to the CuTeGe layer does not proceed sufficiently. Cu composition remains in the conduction path. Since the resistance value after application of the erase voltage depends on the Cu composition distribution remaining in the conduction path, it is considered that the erase resistance value varied as a result.

  From the above analysis results, it is concluded that it is necessary to control the crystallographic structure of the conduction path to be amorphous in order to reduce the variation in the erase resistance value.

In the above embodiment, attention is paid to the dependency of the erase resistance value on the write current, but the direct cause of the resistance value variation is the crystallographic structure of the conduction path.
Even with factors other than the write current, factors that affect the temperature rise of the conduction path during writing and the Cu composition in the conduction path, such as the write voltage, the elemental composition ratio in the ion source, the thermal conductivity of the constituent materials, etc. The crystallographic structure of the conduction path can be affected.
In any case, the variation in resistance value depends on the crystallographic structure of the conduction path, and the variation in resistance value can be suppressed small by controlling the conduction path to be amorphous.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of a memory element that constitutes a memory device according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the memory element in FIG. 1. FIG. 2 is an enlarged cross-sectional view of a main part of the memory element of FIG. It is an EDX mapping image of sample 1 in the initial state. It is an EDX mapping image of the writing state of sample 1. It is an EDX mapping image of the erased state of sample 1. It is an EDX mapping image of the writing state of sample 2. It is an EDX mapping image of the erased state of sample 2. A is an electron diffraction pattern of the conduction path of sample 1. FIG. B is an electron diffraction pattern of the conduction path of sample 2. A is an integrated distribution of resistance values in each state of sample 1. B is an integrated distribution of resistance values in each state of sample 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Memory layer, 3 Ion source layer, 4 Upper electrode, 10 Resistance change element (memory cell), 14 Gate electrode, 31 Conduction path, Tr MOS transistor, BL bit line, WL word line, PL plate electrode

Claims (4)

A storage layer made of an amorphous rare earth element oxide is disposed between the two electrodes, and a layer containing any metal element selected from Cu, Ag, and Zn is provided in contact with the storage layer. With a storage element
By applying a voltage between the two electrodes, a conduction path containing the metal element is formed in a local region in the memory layer of the memory element, and the crystallographic structure of the conduction path is a crystal. A storage device in which the amount of current flowing through the storage element is controlled so that the amorphous state is maintained without being formed . The memory device according to claim 1, wherein the metal element-containing layer of the memory element further includes any element selected from Te, S, and Se. 3. The storage device according to claim 1, wherein the conduction path is formed by applying a voltage so that an electrode side in contact with the layer containing the metal element of the storage element is positive. The storage device according to any one of claims 1 to 3, wherein the rare earth element is at least one selected from Y, La, Nd, Sm, Gd, Tb, and Dy.