JP2007157941A - Storage element and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage element which has good data-holding characteristics. <P>SOLUTION: The storage element 10 has a configuration wherein a storage layer 3 is arranged between a first electrode 2 and a second electrode 6, an ion source layer 4 containing any element selected from Cu, Ag, and Zn is provided in contact with the storage layer 3, and the storage layer 3 is formed of one or more kinds of oxides selected from NiO, CoO, and CeO<SB>2</SB>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and is one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

Furthermore, various non-volatile memories using a crystalline oxide material have also been proposed. For example, a Cr-doped SrZrO ₃ crystal material is sandwiched between a lower electrode made of SrRuO ₃ or Pt and an upper electrode made of Au or Pt. In a device having a structure, there has been reported a memory in which resistance is reversibly changed by application of voltages having different polarities (see Non-Patent Document 2). However, the details such as the principle are unknown.
Special Table 2002-536840 Publication Nikkei Electronics January 20, 2003 issue (page 104) A. Beck et al., Appl. Phys. Lett., 77, (2000), p. 139

  However, the above-described memory element having a structure in which either the upper electrode or the lower electrode contains Cu, Ag, Zn and GeS or GeSe amorphous chalcogenide material is sandwiched between these electrodes, or memory using a crystalline oxide material The element has a very large resistance on / off ratio, that is, a ratio of a resistance value in a low resistance state (on resistance) to a resistance value in a high resistance state (off resistance), for example, four or more digits.

When a short voltage pulse is applied to a memory element having a very large resistance on / off ratio, an intermediate value of these resistance values may be obtained.
If the resistance value of the memory element takes an intermediate value, the data identification margin decreases at the time of reading.

The problem that the resistance value takes an intermediate value is that the film thickness of a thin film with variable resistance, for example, GeS, GeSe, etc. is relatively thick (for example, 10 nm or more). For this reason, it is considered that the result is that atoms such as Cu, Ag, and Zn that should move as ions do not move between certain positions but are trapped in the middle. In addition, since the thickness of the thin film whose resistance changes is relatively large, the operation speed of the memory element is reduced.
Furthermore, since the electric field strength during recording / erasing operation is weakened, the energy level at which ion atoms after movement (transition from the ionic state to the non-ionic state after the recording or erasing process) resumes moving. As a result, it becomes difficult to secure sufficient data retention characteristics necessary for the nonvolatile memory.

  In order to solve the above-described problems, the present invention provides a memory element with good data retention characteristics and a memory device using the same.

In the memory element of the present invention, a memory layer is disposed between the first electrode and the second electrode, and ions containing any element selected from Cu, Ag, and Zn are in contact with the memory layer. source layer is provided, in which the storage layer is NiO, CoO, consisting of one or more oxides selected from CeO _2.
A memory device of the present invention includes the memory element of the present invention, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. Is.

  According to the configuration of the memory element of the present invention described above, the memory layer is disposed between the first electrode and the second electrode, and any one selected from Cu, Ag, and Zn is in contact with the memory layer. Since the ion source layer containing the element is provided, information can be recorded by utilizing the change in the resistance state of the memory layer.

Specifically, for example, when a positive potential is applied to the ion source layer itself containing Cu, Ag, Zn, or the electrode side in contact with the ion source layer and a voltage is applied to the memory element, Cu, Ag, Zn (ion source element) is ionized and diffuses into the memory layer and is combined with electrons at the other electrode side and deposited, or the impurity level of the insulating film staying in the memory layer is reduced. By forming, the resistance value of the memory layer is lowered, and thus information can be recorded.
Further, from this state, when a negative potential is applied to the ion source layer containing Cu, Ag, Zn or one electrode in contact with the ion source layer and a negative voltage is applied to the memory element, it is deposited on the other electrode side. Since Cu, Ag, and Zn are ionized again and return to one electrode side, the resistance value of the memory layer returns to the original high state, and the resistance value of the memory element also increases, so that the recorded information is erased. It becomes possible to do.

The storage layer is made of one or more kinds of oxides selected from NiO, CoO, and CeO ₂ , so that the resistance state can be stably maintained even in a high temperature environment and the like, and the data retention characteristic is good. .
In addition, it is possible to record information in the storage layer even by a voltage pulse having a short pulse width.
Furthermore, since the heat resistance of the memory layer can be improved by using the above-described oxide, the manufacturing yield of the memory element under a high temperature process can be improved, and the operation of the memory element such as recording / erasing can be improved. It is possible to improve the stability against a local temperature rise at the time, for example, to increase the number of times that rewriting can be repeated.
Furthermore, since the memory layer made of the above oxide has a sufficient withstand voltage even if the film thickness is reduced, a high resistance state can be easily realized and defects such as pinholes can be reduced. Therefore, information recording can be performed stably.

  According to the configuration of the memory device of the present invention described above, the memory element of the present invention, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, By arranging a large number, the current can be passed from the wiring to the storage element, and information can be recorded or erased.

According to the above-described present invention, since the memory element has good data retention characteristics and can stably retain information recorded in the memory layer, the reliability of the memory element can be improved. .
In addition, since information can be recorded by a voltage pulse having a short pulse width, information can be recorded at high speed.

  Furthermore, since information is recorded by utilizing a change in the resistance value of the memory element, in particular, a change in the resistance value of the memory layer, even when the memory element is miniaturized, the information is recorded or recorded information. It has the advantage that the holding | maintenance of becomes easy.

Therefore, according to the present invention, a highly reliable storage device can be configured.
In addition, the storage device can be highly integrated (densified) and downsized.

  First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.

In the memory element described above, the thin film (memory thin film) that becomes a recording layer on which information is recorded by changing the resistance can easily realize a high resistance state and has fewer defects such as pinholes. Thus, it is desirable that sufficient insulation resistance can be obtained even though the film is very thin.
In the low resistance state (ON state), a relatively large current density of current flows and Joule heat is generated, and the operation is performed in a considerably high temperature state. It is desirable that

  It is desirable to select a material for the storage layer so that the storage element has good data retention characteristics.

Therefore, in the present invention, one or more kinds of oxides selected from NiO, CoO, and CeO ₂ (each oxide alone or a mixture of two or more kinds) are used for the memory layer of the memory element.
As a result, the resistance state can be stably maintained even in a high temperature environment and the like, and the data retention characteristic is good. In addition, it is possible to record information in the storage layer even by a voltage pulse having a short pulse width.
Further, sufficient insulation resistance can be obtained even with a very thin film, and since the melting points of these oxides are relatively high, the memory element can be stably operated even at a high temperature.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element is shown in FIG.
In the memory element 10, a lower electrode 2 is formed on a substrate 1 having a high electrical conductivity, for example, a (P ⁺⁺ ) silicon substrate 1 doped with a P-type high-concentration impurity, and insulation on the lower electrode 2 is performed. A memory thin film (memory layer) 3 having a relatively high resistance value is formed so as to be connected to the lower electrode 2 through the opening formed in the layer 5, and Cu, Ag, Zn, and the like are formed on the memory thin film 3. An ion source layer 4 containing any element of Te, S, and Se is formed, and an upper electrode 6 is formed on the ion source layer 4.

For the lower electrode 2, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, WN, TaN, silicide, or the like can be used.
For example, when a W film is used for the lower electrode 2, the film thickness may be in the range of 10 nm to 100 nm, for example.

  In addition, the ion source layer 4 contains at least one of Cu, Ag, Zn, and at least one of Te, Se, S chalcogenide elements, CuTe, GeSbTe, CuGeTe, AgGeTe, AgTe, ZnTe, ZnGeTe. , CuS, CuGeS, CuSe, CuGeSe, and the like, and further, boron or a rare earth element and silicon can be used to form the ion source layer 4.

In particular, the portion where the resistance value changes is limited to the memory thin film (memory layer) 3 having a relatively high resistance value, and a material having a sufficiently low resistance compared to the high resistance memory thin film 3 (for example, Te is preferably used as the chalcogenide element of the ion source layer 4 from the viewpoint of lowering the resistance value when the memory thin film 3 is on), and Cu, Ag, It is desirable to form the ion source layer 3 from a material containing Zn, which contains CuTe, AgTe, and ZnTe as a main component.
Further, when Cu is used as an element that becomes a cation of the ion source layer 4 and CuTe is included, the resistance of the ion source layer 4 is lowered to reduce the resistance change of the ion source layer 4 (memory layer). 3 is more preferable because it can be made sufficiently smaller than the resistance change of 3, and the stability of the memory operation can be improved.
For example, when a CuGeTe film is used for the ion source layer 4, the film thickness may be set to 5 nm to 50 nm, for example.

The insulating layer 5 includes, for example, a hard-cured photoresist, SiO ₂ or Si ₃ N ₄ generally used for semiconductor devices, and other materials such as SiON, SiOF, Al ₂ O ₃ , Ta ₂ O ₅ , Inorganic materials such as HfO ₂ and ZrO ₂ , fluorine organic materials, aromatic organic materials, and the like can be used.
As with the lower electrode 2, a normal semiconductor wiring material is used for the upper electrode 6.

In the memory element 10 of the present embodiment, in particular, the memory thin film (memory layer) 3 is composed of one or more kinds of oxides selected from NiO, CoO, and CeO ₂ .
As a result, the resistance state of the memory thin film (memory layer) 3 can be stably maintained even in a high temperature environment, so that the memory element 10 has good data retention characteristics. Further, writing and erasing can be performed on the storage layer 3 even by a voltage pulse having a short pulse width.
Furthermore, since these oxides have a high melting point, the microstructure of the memory thin film (memory layer) 3 can be stabilized against a temperature rise.
Thereby, since the heat resistance of the memory thin film (memory layer) 3 can be improved, the manufacturing yield of the memory element 10 under a high temperature process can be improved.
Further, it is possible to improve the stability against a local temperature rise during the operation of the storage element 10 such as recording (writing, erasing), and to increase the number of times that rewriting can be repeated, for example.

Further, the memory thin film (memory layer) 3 made of the above-described oxide has a sufficient withstand voltage even when the film thickness is reduced.
Thus, a high resistance state can be easily realized and defects such as pinholes can be reduced, so that information can be recorded stably.

The film thickness of the memory thin film (memory layer) 3 is preferably in the range of 1 nm to 10 nm, although it depends on the oxide material used.
If the film thickness of the memory thin film (memory layer) 3 is too thin, it becomes difficult to form a film in a good state due to the influence of the surface roughness of the lower electrode 2, and if it is too thick, the movement distance of ions increases. The speed is slow.

Note that the memory thin film (memory layer) 3 may contain a small amount of other elements in addition to the oxides (NiO, CoO, CeO ₂ ) described above.

  The storage element 10 of this embodiment can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 4 containing Cu, Ag, and Zn, and a positive voltage is applied to the memory element 10 so that the upper electrode 6 side becomes positive. . As a result, Cu, Ag, Zn is ionized from the ion source layer 4 and diffuses in the memory thin film 3, and is combined with electrons on the lower electrode 2 side to deposit, or in the memory thin film 3. Stays diffuse.
Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the memory thin film 3, or a large number of defects due to Cu, Ag, Zn are formed inside the memory thin film 3, whereby the memory thin film The resistance value of 3 becomes low. Each layer other than the memory thin film 3 originally has a lower resistance value than the resistance value of the memory thin film 3 before recording. Therefore, by reducing the resistance value of the memory thin film 3, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. As a result, information can be recorded (written) (recording process).

On the other hand, for example, a negative potential (−potential) is applied to the ion source layer 4 containing Cu, Ag, and Zn, and a negative voltage is applied to the memory element 10 so that the upper electrode 6 side becomes negative. . As a result, Cu, Ag, and Zn constituting the current path or impurity level formed in the memory thin film 3 are ionized, move in the memory thin film 3, and return to the ion source layer 4 side.
Then, current paths or defects due to Cu, Ag, and Zn disappear from the memory thin film 3, and the resistance value of the memory thin film 3 increases. Since each layer other than the memory thin film 3 originally has a low resistance value, the resistance value of the memory element 10 as a whole can be increased by increasing the resistance value of the memory thin film 3.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. This makes it possible to erase the recorded information (erase process).

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

In particular, the ion source layer 4 contains an element selected from Te, S, Se, that is, a chalcogen element in addition to the above-described metal elements (Cu, Ag, Zn), so that the metal element in the ion source layer 4 is obtained. (Cu, Ag, Zn) and a chalcogen element (Te, S, Se) are combined to form a metal chalcogenide layer. The metal chalcogenide layer mainly has an amorphous structure. For example, when a positive potential is applied to the side of the upper electrode 6 in contact with the ion source layer 4 made of the metal chalcogenide layer, the metal element contained in the metal chalcogenide layer (Cu, Ag, Zn) is ionized and diffused into the memory thin film 3 exhibiting high resistance, and is combined with electrons at a part on the lower electrode 2 side and deposited, or in the memory thin film 3 By forming the impurity level of the insulating film, the resistance of the memory thin film 3 is lowered, and information can be recorded.
From this state, when a negative potential is applied to the upper electrode 6 side in contact with the ion source layer 4 made of a metal chalcogenide layer, the metal elements (Cu, Ag, Zn) deposited on the lower electrode 2 side are ionized again, By returning to the metal chalcogenide layer, the resistance of the memory thin film 3 returns to the original high state, and the resistance of the memory element 10 also increases, so that the recorded information can be erased.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

The memory thin film 3 generally has a high resistance in the initial state before recording. However, the memory thin film 3 exhibits a low resistance in the initial recording state by plasma treatment, annealing treatment, or the like in the process step. It doesn't matter.
The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the memory thin film 3, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recorded data, it is sufficient that the ratio of the initial resistance value and the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance value after recording. Is 50 Ω, or the resistance value before recording is 100 kΩ and the resistance value after recording is 50 kΩ, and the initial resistance value of the memory thin film 3 is set to satisfy such a condition. . The resistance value of the memory thin film 3 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials.

  According to the configuration of the memory element 10 of the above-described embodiment, by adopting a configuration in which the memory thin film 3 and the ion source layer 4 are sandwiched between the lower electrode 2 and the upper electrode 6, for example, When a positive voltage (+ potential) is applied to the ion source layer 4 side so that the upper electrode 6 side becomes positive, a current path containing a large amount of Cu, Ag, and Zn is formed in the memory thin film 3. In addition, by forming a large number of defects due to Cu, Ag, and Zn in the memory thin film 3, the resistance value of the memory thin film 3 is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded.

  Further, for example, a negative voltage (−potential) is applied to the ion source layer 4 with respect to the storage element 10 in the state after recording, so that the upper electrode 6 side becomes negative. As a result, current paths or defects due to Cu, Ag, and Zn formed in the memory thin film 3 disappear, the resistance value of the memory thin film 3 increases, and the resistance value of the entire memory element 10 increases. Become. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

  Since information is stored by utilizing a change in the resistance value of the memory element 10, particularly a change in the resistance value of the memory thin film 3, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

In addition, according to the memory element 10 of the present embodiment, the memory thin film (memory layer) 3 is made of one or more kinds of oxides selected from NiO, CoO, and CeO _2. Etc., the resistance state can be stably maintained, and it has good data retention characteristics. Information can be recorded (written or erased) on the storage layer 3 even by a voltage pulse having a short pulse width.
Furthermore, since the heat resistance of the memory layer 3 can be improved by using the above-described oxide, the manufacturing yield of the memory element 10 under a high temperature process can be improved and recording (writing, erasing) can be performed. It is possible to improve the stability against a local temperature rise during the operation of the storage element 10 such as, for example, to increase the number of times that rewriting can be repeated.
Furthermore, the memory thin film (memory layer) 3 made of the above-mentioned oxide has a sufficient withstand voltage even if the film thickness is reduced, so that a high resistance state can be easily realized and a pinhole or the like can be realized. Therefore, information can be recorded stably.

Further, according to the memory element 10 of the present embodiment, the lower electrode 2, the memory thin film 3, the ion source layer 4, and the upper electrode 6 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

In the memory element 10 of the above-described embodiment, the oxide thin film 3 of the memory thin film 3 is formed by a method using an oxide sputtering target or an inert gas such as argon as an introduced gas during sputtering using a metal target. It can be formed by using a method of introducing oxygen together with a gas, a method such as so-called reactive sputtering.
Furthermore, in addition to sputtering, an oxide thin film can be formed by a method such as CVD or vapor deposition. In addition, the film is in a metal state at the time of film formation, and thereafter a method such as thermal oxidation or chemical treatment. It is also possible to form an oxide thin film.

The memory element 10 of FIG. 1 can be manufactured as follows, for example.
First, a lower electrode 2, for example, a W film is deposited on a substrate 1 having high electrical conductivity, for example, a silicon substrate doped with a high concentration of P-type impurities.
Thereafter, the insulating layer 5 is formed so as to cover the lower electrode 2, but a part of the insulating layer 5 is removed by photolithography to form a contact portion to the lower electrode 2.
Next, a memory thin film 3, for example, a nickel oxide (NiO) film is formed, and then an ion source layer 4, for example, a CuTeGe film is formed.
Subsequently, for example, a W film is formed as the upper electrode 6 by, for example, a magnetron sputtering apparatus.
Thereafter, the W film is patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
In this way, the memory element 10 shown in FIG. 1 can be manufactured.

By using the memory element 10 of the above-described embodiment and arranging a large number of memory elements 10 in, for example, a column shape or a matrix shape, a memory device (memory) can be configured.
For each memory element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 6 side are provided. For example, each memory element 10 is arranged near the intersection of these wirings. What should I do?

  Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the upper electrode 6 is formed in common in the memory cell in the column direction, and a current is applied by applying a potential. By selecting the lower electrode 2 and the wiring to be flown, a memory cell to be recorded is selected, and a current is passed through the memory element 10 of this memory cell to record information or erase the recorded information. it can.

The storage element 10 according to the above-described embodiment can easily and stably record information and read information, and has particularly excellent characteristics in high temperature environment and long-term data retention stability. .
Further, even when the memory element 10 according to the above-described embodiment is miniaturized, it becomes easy to record information and hold the recorded information.
Therefore, by configuring the storage device using the storage element 10 of the above-described embodiment, the storage device can be integrated (high density) or downsized.

  In the memory element 10 of the above-described embodiment, the ion source layer 4 and the upper electrode 6 are separately formed of different materials. However, in the present invention, the elements (Cu, Ag) serving as the ion source in the electrode are used. , Zn) may be contained so that the electrode layer and the ion source layer are combined.

  Further, in the memory element 10 of the above-described embodiment, the ion source layer 4 is laminated on the memory thin film 3. However, the order of the lamination is reversed, and the memory thin film is formed on the ion source layer. You may laminate.

(Example)
Next, the memory element was actually fabricated and the characteristics were examined.

<Experiment 1>
A W film having a thickness of 20 nm is deposited as a lower electrode 2 on a silicon wafer, a photoresist film is formed so as to cover the surface, and then exposure and development are performed by a photolithography technique to open (through through) the photoresist. Hole) was formed. Thereafter, annealing was performed in vacuum to alter the photoresist, and the insulating layer 5 was formed as a hard cure resist that was stable with respect to temperature, etching, and the like. An oxide layer to be the memory thin film 4 is formed thereon, then a Cu ₅₀ Te ₃₅ Ge ₁₅ film is formed as the ion source layer 3 with a thickness of 20 nm, and a W film is formed as the upper electrode 6 with a thickness of 100 nm. .
Thereafter, the ion source layer 4 and the upper electrode 6 deposited on the insulating layer 5 made of a hard-cure resist were patterned by a photolithography technique using a plasma etching apparatus. The size of the opening is 0.7 μmφ.
In this way, the memory element 10 having the structure shown in FIG.

And the sample of each memory | storage element 10 was produced by changing the material and film thickness of the oxide layer of the memory thin film 3 with the above-mentioned manufacturing method.
The breakdown is NiO film (film thickness 1 nm, 2 nm, 3 nm), Al ₂ O ₃ film (film thickness 1 nm, 2 nm, 3 nm), CoO film (film thickness 1.5 nm, 3 nm, 5 nm), CeO ₂ film (film thickness). 12 types in total (1 nm, 3 nm, 5 nm).

(IV characteristics)
The IV characteristics were measured for each of these samples.
The IV measurement was performed as follows.
For the memory element 10 of each sample, the back surface of the low-resistance silicon substrate 1 electrically connected to the lower electrode 2 was connected to the ground potential (ground potential), and a positive potential (+ potential) was applied to the upper electrode 6. .
Then, the positive potential applied to the upper electrode 6 was increased from 0 V, and the change in current was measured. However, the current limiter is set to operate when the current reaches 1.5 mA, and the positive potential applied to the upper electrode 6, that is, the absolute value of the voltage applied to the memory element is not increased beyond that. Set to.
Further, from the state where the current reached 1.5 mA and the current limiter was operated, the positive potential applied to the upper electrode 6 was decreased to 0 V, and the change in current was measured. Subsequently, on the contrary, a negative potential was applied to the upper electrode 6 to increase the application of the negative voltage to such a voltage that the current decreased and no current flowed, and then the operation was returned to the zero potential again.

A typical example of the IV characteristics obtained in this way is shown in FIG. In FIG. 2, the IV characteristics of the two samples are indicated by a solid line and a broken line, respectively.
Then, as shown in FIG. 2, a voltage when a positive voltage is first applied to the upper electrode 6 and the resistance value changes from a high resistance to a low resistance is defined as an “initial write voltage”.
Further, in the process of increasing the voltage from 0 V to the initial write voltage, a minute current when a voltage of 1 V is applied is defined as a leakage current.

For each sample of the memory element, an initial write voltage and a leak current were obtained from the measured IV characteristics. However, when the initial write voltage is less than 1 V, the current that flows when the initial write voltage is applied is used as the leakage current.
As a measurement result, FIG. 3A shows the relationship between the film thickness of the memory thin film 3 and the initial write voltage, and FIG. 3B shows the relationship between the film thickness of the memory thin film 3 and the leakage current.

  From FIG. 3A, when NiO is used, the initial write voltage does not increase so much even if the film thickness is 3 nm. That is, it can be seen that it is advantageous in that the write voltage can be suppressed.

As shown in FIG. 3B, when Al ₂ O ₃ is used, even in a thin film thickness region, a leakage current is very small compared to the others, and a current required for reading can be reduced. From this point, it can be seen that it is advantageous.

Regarding the film thicknesses of various oxide films used for the memory thin film 3, the lower limit is considered to be about 1 nm in consideration of the surface roughness of the lower electrode 2. If the oxide film is too thin, it is difficult to form a good film.
Further, from the viewpoint of the power supply voltage or the like of the memory IC or the like, the write voltage is preferably less than 3 V, and the upper limit of the film thickness of the memory thin film 3 is determined therefrom.
It should be noted that, like NiO, the dependence on the film thickness is small, and even if the oxide film is thickened to some extent, the thickness is desirably 10 nm or less even when the write voltage is less than 3V. This is because the memory element of the present invention performs the writing operation and the erasing operation by the movement of ions, and the oxide film as the memory layer 3 corresponds to the movement distance of the ions. This is because the speed becomes slow.
From the above, it is desirable that the thickness of each oxide film is set within the range shown in Table 1.

<Experiment 2>
Instead of the memory element 10 shown in FIG. 1, as another embodiment of the present invention, the memory element 20 shown in FIG. 4 was fabricated and the characteristics were examined.
The memory element 20 shown in FIG. 4 has the same basic laminated structure as the memory element 10 of the previous embodiment shown in FIG. 1, but the lower electrode 2 is formed in a smaller pattern and the insulating film 5 Embedded in the opening formed.

The memory element 20 having such a configuration can be manufactured as follows.
An insulating film (for example, Al ₂ O ₃ , Ta ₂ O _5, etc.) 5 is uniformly deposited on the silicon substrate 1 having a low resistivity by sputtering, and then a lower electrode formation pattern (pattern portion is formed by photolithography). (Without resist) is formed of a photoresist, and then the insulating film 5 is partially removed by RIE (Reactive Ion Etching).
Next, a material (for example, W) for forming the lower electrode 2 is uniformly deposited by sputtering. Thereafter, the surface is processed by CMP (Chemical Mechanical Polishing) method or etch back method to flatten the surface so that the lower electrode material remains only in the lower electrode formation pattern. Thereby, the lower electrode 2 is formed in a predetermined pattern.
Next, each layer of the memory thin film (memory layer) 3, the ion source layer 4, and the upper electrode 6 is continuously formed by sputtering.
Thereafter, these films 3, 4, and 6 are patterned by photolithography and etching, whereby the memory element 20 having the structure of FIG. 4 can be manufactured.

Then, by the manufacturing method described above, a W film is deposited as a lower electrode 2 to a thickness of 200 nm on a silicon wafer, and various oxide films (NiO film, Al ₂ O ₃ film, CoO) are deposited thereon as a memory thin film 3. Film, CeO ₂ film), Cu ₅₀ Te ₃₅ Ge ₁₅ film as the ion source layer 4 with a film thickness of 20 nm, and W film as the upper electrode 6 with a film thickness of 200 nm. A sample of the memory element 20 shown in FIG. 4 was prepared for the film.
The insulating film 5 was a silicon oxide film, and the size of the lower electrode formation pattern was about 0.3 μmφ.
The thickness of each oxide film was set to the value shown in Table 2.

(Write characteristics)
A writing operation and an erasing operation using a pulse voltage were performed on each sample of these memory elements 20.
In addition, writing with a pulse voltage was performed while changing the pulse width, and the shortest pulse width that can be written was examined.
The results are shown in FIG.

From FIG. 5, the case where NiO was used was the shortest, and writing was successful even with a pulse voltage of 10 ⁻⁸ seconds (10 n seconds).
Further, even when the longest CoO is used, writing can be performed with a pulse voltage of less than 10 ⁻⁶ seconds (1 μsec), so that a sufficient operation speed can be ensured.

(Data retention characteristics)
Next, data retention characteristics were confirmed.
In samples using various oxide films, 20 memory elements each written with a pulse voltage having a pulse width of 1 μs (low resistance state) and 20 memory elements erased after writing (high resistance state) were prepared. In this state, heat treatment was performed at 200 ° C. for 1 hour.
In each memory element, the resistance value states before and after the heat treatment were compared, and the ratio at which the low resistance state or the high resistance state was maintained was examined.
Then, the memory element 20 using various oxide films as the memory thin film 3 with the product (0-1) of the write retention ratio (0-1) and the erase retention ratio (0-1) after the heat treatment as an index. Sought indicators for each. For example, when the write retention ratio is 0.7 and the erase retention ratio is 0.8, the index is 0.56.
As a result, the index is converted into percentage (%) and shown in FIG.

As can be seen from FIG. 6, the index of NiO is particularly high at 100%, and even in CeO ₂ and CoO, data of 85% or more is retained even after heat treatment, which is advantageous from the viewpoint of data retention characteristics. I understand that.

(High temperature process resistance)
Table 3 shows melting points of various oxide films used for the memory thin film 3 in Experiment 2. Table 3 also shows melting points for HfO ₂ and SiO ₂ .

From Table 3, it can be seen that the melting point of HfO ₂ is the highest and the change is expected to be very small even for a high temperature process, which is advantageous in this respect.
In addition, since the melting point of SiO ₂ used for the insulating layer 5 and the like is 1710 ° C., CeO ₂ , Al ₂ O ₃ , and NiO have higher melting points than SiO ₂ and have higher heat resistance than SiO _2. Therefore, the change is expected to be small even for a high temperature process.

Note that CoO has a lower melting point than SiO ₂ but has a melting point of 1451 ° C., so that it is considered that no problem occurs in the normal manufacturing process of the memory element.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of the memory element of one embodiment of this invention. It is a typical example of the IV characteristic of the memory element of FIG. It is a figure which shows the relationship between the film thickness of A thin film for memory | storage, and an initial stage write voltage. B is a diagram showing the relationship between the thickness of the memory thin film and the leakage current. It is a schematic block diagram (sectional drawing) of the memory element of other embodiment of this invention. It is the figure which compared the minimum pulse width which can be written in the case of using various oxides. It is the figure which compared the data retention parameter | index after heat processing at the time of using various oxides.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower electrode, 3 Memory thin film (memory layer), 4 Ion source layer, 5 Insulating layer (insulating film), 6 Upper electrode, 10, 20 Memory element

Claims (5)

A memory layer is disposed between the first electrode and the second electrode,
An ion source layer containing any element selected from Cu, Ag, and Zn is provided in contact with the storage layer,
Storage elements wherein the storage layer is to, NiO, CoO, characterized in that it consists of one or more oxides selected from CeO _2.   The memory element according to claim 1, wherein the ion source layer contains any element selected from Te, S, and Se.   The memory element according to claim 1, wherein the ion source layer comprises CuTe.   The memory element according to claim 1, wherein the thickness of the memory layer is in a range of 1 nm to 10 nm. A memory layer is disposed between the first electrode and the second electrode, and in contact with the memory layer, any element selected from Cu, Ag, Zn, and any element selected from Te, S, Se An ion source layer containing such an element, and the storage layer is made of one or more oxides selected from NiO, CoO, and CeO ₂ ;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device comprising a large number of the storage elements.

Images