JP4815804B2 - Storage element and storage device - Google Patents

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

Furthermore, various non-volatile memories using a crystalline oxide material have also been proposed. For example, a Cr-doped SrZrO ₃ crystal material is sandwiched between a lower electrode made of SrRuO ₃ or Pt and an upper electrode made of Au or Pt. In a device having a structure, there has been reported a memory in which resistance is reversibly changed by application of voltages having different polarities (see Non-Patent Document 2). However, the details such as the principle are unknown.
Special Table 2002-536840 Publication Nikkei Electronics January 20, 2003 issue (page 104) A. Beck et al., Appl. Phys. Lett., 77, 2000, p. 139

  However, in the memory element having a structure in which Cu, Ag, or Zn is contained in either the upper electrode or the lower electrode and GeS or GeSe amorphous chalcogenide material is sandwiched between the electrodes, the chalcogenide thin film is crystallized due to temperature rise. The characteristics of the material changed with crystallization, and the data was originally held in a high resistance state, but it changed to a low resistance state in a high temperature environment or during long-term storage. Have a problem.

For example, when a crystalline material is used as the recording material between the upper electrode and the lower electrode, there are more problems than when an amorphous material is used, and it is difficult to perform mass production at a low price.
In addition, in order to obtain good crystallinity, it is necessary to perform a high temperature treatment such as 700 ° C., which causes a problem that the characteristics of the MOS transistor formed in advance are deteriorated by heat.
In addition, in order to perform crystal growth, a base material is limited, and for example, it is necessary to use a single crystal material.

  Furthermore, for example, when a crystal material such as a single crystal material is used as the base material, the reason is unknown, but the switching voltage applied when switching from the high resistance state to the low resistance state is likely to vary. There was also a problem.

  In order to solve the above-described problem, in the present invention, a storage element having a configuration that can easily and stably record and read information and can be easily manufactured by a relatively simple manufacturing method, and the same The present invention provides a storage device using the.

The memory element of the present invention is configured such that a memory layer and an ion source layer are sandwiched between a first electrode and a second electrode, and the ion source layer contains Cu, Te, and boron. It is.

According to the configuration of the memory element of the present invention described above, the memory layer and the ion source layer are sandwiched between the first electrode and the second electrode, and Cu and Te are formed on the ion source layer. Therefore, information can be recorded by utilizing the change in the resistance state of the storage layer.

Specifically, for example, when a positive potential is applied to the ion source layer itself containing Cu or the electrode side in contact with the ion source layer and a voltage is applied to the memory element, Cu (ion source element) contained in the ion source layer Is ionized and diffused in the memory layer and combined with electrons in the other electrode side and deposited, or by staying in the memory layer and forming an impurity level of the insulating film, The resistance value is lowered, which makes it possible to record information.
Also, from this state, when a negative potential is applied to the ion source layer containing Cu or one electrode in contact with the ion source layer and a negative voltage is applied to the memory element, the Cu deposited on the other electrode side is again By ionizing and returning to one electrode side, the resistance value of the memory layer returns to the original high state, and the resistance value of the memory element also increases, so that the recorded information can be erased.

Further, since Te (chalcogenide element) is contained in the ion source layer, the ionization of Cu is promoted.

Further, since the ion source layer further contains boron, crystallization of the ion source layer is suppressed, so that the ion source layer has a uniform amorphous structure, or has a very small particle diameter and a uniform size. Therefore, even if heat is applied to the memory element in the heat treatment process, the fine structure of the ion source layer is kept stable, and the film state (surface state, etc.) of the ion source layer is good. Maintained in a state. That is, the fine structure of the ion source layer can be kept stable even in a semiconductor process, particularly in a high-temperature heat treatment process required in a wiring process.
As a result, when recording and erasing information, the electric field distribution in the storage layer becomes uniform, and the voltage threshold (switching voltage) when changing the storage element from the high resistance state to the low resistance state varies. Since it can be reduced, a uniform value can be obtained even when recording and erasing are repeated.
That is, even after the high temperature heat treatment is performed, the ion source layer and the memory layer can be kept in a good state, and the heat resistance of the memory element can be improved.

The memory element of the present invention is configured by sandwiching a memory layer and an ion source layer between a first electrode and a second electrode, and this ion source layer contains Cu, Te, a rare earth element, and silicon. It is what has been.

According to the configuration of the memory element of the present invention described above, the memory layer and the ion source layer are sandwiched between the first electrode and the second electrode, and the ion source layer includes Cu and Te. Therefore, information can be recorded by utilizing the change in the resistance state of the memory layer.
Further, since Te (chalcogenide element) is contained in the ion source layer, the ionization of Cu is promoted.
The ion source layer further contains rare earth elements and silicon, thereby suppressing the crystallization of the ion source layer due to the application of heat, and the ion source layer contains boron. Similarly, since the ion source layer and the memory layer can be kept in a good state, the heat resistance of the memory element can be improved.

The memory device of the present invention is configured such that a memory layer and an ion source layer are sandwiched between a first electrode and a second electrode, and Cu, Te and boron are contained in the ion source layer. It has a memory element, wiring connected to the first electrode side, and wiring connected to the second electrode side, and a large number of memory elements are arranged.

  According to the configuration of the memory device of the present invention described above, the memory element according to the present invention described above, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, Since a large number of memory elements are arranged, information can be recorded and information can be erased by supplying current from the wiring to the memory elements.

The memory device of the present invention is configured by sandwiching a memory layer and an ion source layer between a first electrode and a second electrode, and this ion source layer contains Cu, Te, a rare earth element, and silicon. The memory element, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, and a large number of memory elements are arranged.

  According to the configuration of the memory device of the present invention described above, the memory element according to the present invention described above, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, Since a large number of memory elements are arranged, information can be recorded and information can be erased by supplying current from the wiring to the memory elements.

According to the present invention, even when heat is applied to the memory element by a high-temperature heat treatment process or the like, information can be recorded / erased on the memory element repeatedly and stably.
The structure of the memory element can be manufactured by a simple method as compared with other types of memory elements (memory elements such as a semiconductor memory and a ferroelectric memory).

  Furthermore, since information is recorded by utilizing the change in resistance value of the memory element, there is an advantage that even when the memory element is miniaturized, it is easy to record information and hold the recorded information. is doing.

Therefore, according to the present invention, information can be stably recorded and erased, and a storage device that can be easily manufactured by a relatively simple manufacturing method can be configured.
In addition, the storage device can be highly integrated (densified) and downsized.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element is shown in FIG.
In this memory element 10, a lower electrode 2 is formed on a substrate 1 having a high electrical conductivity, for example, a P-type high concentration impurity doped (P ⁺⁺ ) silicon substrate 1, and a Cu electrode is formed on the lower electrode 2. , Ag, Zn and any element of Te, S, Se are formed, the ion source layer 3 is formed, and the memory thin film (memory layer) 4 is formed thereon, and this memory thin film 4 An upper electrode 6 is formed so as to be connected to the memory thin film 4 through an opening formed in the upper insulating layer 5.

In the memory element 10 of this embodiment, in particular, the ion source layer 3 is configured to further contain boron B in addition to the above-described Cu, Ag, Zn, and Te, S, Se.
Instead of containing boron B, the ion source layer 3 may contain a rare earth element and silicon Si. As the rare earth elements, various rare earth elements such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y can be contained in the ion source layer 3.
Note that two types of elements including boron B and rare earth elements or silicon Si may be included in the ion source layer 3, and these three types (boron B, rare earth elements, silicon Si) may be included in the ion source. It may be contained in the layer 3.
By containing these elements in the ion source layer 3, the stability of the memory element against heat treatment, that is, the heat resistance can be improved.

For the lower electrode 2, a wiring material used in a semiconductor process, for example, TiW, Ti, W, WN, Cu, Al, Mo, Ta, TaN, silicide, or the like can be used.
When a TiW film, for example, is used for the lower electrode 2, the film thickness may be in the range of 10 nm to 100 nm, for example.

The ion source layer 3 includes at least one of Cu, Ag, Zn, and at least one of Te, Se, S chalcogenide elements, CuTe, GeSbTe, CuGeTe, AgGeTe, AgTe, ZnTe, ZnGeTe. , CuS, CuGeS, CuSe, CuGeSe, etc., and further, boron, or a rare earth element and silicon can be used to form the ion source layer 3.
For example, when a CuGeTeBGd film is used for the ion source layer 3, the film thickness may be set to 5 nm to 50 nm, for example.

The memory thin film (memory layer) 4 has a high resistance, and as a guide, if it is more than twice the ON resistance of the selection MOS transistor, there is no problem in the memory operation, and an insulating thin film or a semiconductive film is used. For example, a rare earth oxide film, a rare earth nitride film, a silicon oxide film, a silicon nitride film, or the like is used.
This memory thin film 4 is formed with a film thickness of 0.5 nm or more and 10 nm or less. By forming the memory thin film 4 with such a film thickness, the amorphous state can be stably formed at a high temperature, and the resistance value can be increased and stabilized. As a result, as shown in Experiment 7 to be described later, a stable recording operation can be performed.
In addition, since a material such as a rare earth oxide thin film is usually an insulating film, a semiconductive state can be obtained by making the film thickness extremely thin, for example, 5 nm or less.

Further, the composition of oxygen in the memory thin film 4 is usually a composition of RE ₂ O ₃ with respect to the rare earth element (RE), but here it is an amorphous film having a conductivity lower than that of the semiconductor region. Since it is sufficient if it has electrical properties, it is not necessarily limited to such a composition. For example, REOx (0.5 <x ≦ 1.5) may be used.

  In addition, the memory thin film 4 includes elements other than rare earth elements such as Ge, Sb, Ti, W, Cu, Ag, Zn, Fe, Co, P, N, H, Te, S, and Se. It may be contained in advance.

  The memory thin film 4 made of the above-described material has a characteristic that the impedance (resistance value) changes when a voltage pulse or a current pulse is applied.

The insulating layer 5 includes, for example, a hard-cured photoresist, SiO ₂ or Si ₃ N ₄ generally used for semiconductor devices, and other materials such as SiON, SiOF, Al ₂ O ₃ , Ta ₂ O ₅ , Inorganic materials such as HfO ₂ and ZrO ₂ , fluorine organic materials, aromatic organic materials, and the like can be used.
As with the lower electrode 2, a normal semiconductor wiring material is used for the upper electrode 6.
In the memory element 10 shown in FIG. 1, the memory thin film 4 is formed on the ion source layer 3, but the ion source layer 3 may be formed on the memory thin film 4.
Alternatively, the upper electrode 6 may be formed by laminating an electrode layer directly on the memory thin film 4 and patterning it in a predetermined pattern.

  The storage element 10 of this embodiment can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 3 containing Cu, Ag, and Zn, and a positive voltage is applied to the memory element 10 so that the upper electrode 6 side becomes negative. . As a result, Cu, Ag, Zn is ionized from the ion source layer 3 and diffuses in the memory thin film 4, and is combined with electrons on the upper electrode 6 side to be deposited, or in the memory thin film 4. Stays diffuse.
Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the memory thin film 4 or a large number of defects due to Cu, Ag, Zn are formed inside the memory thin film 4, so that the memory thin film The resistance value of 4 becomes low. Each layer other than the memory thin film 4 originally has a lower resistance value than the resistance value of the memory thin film 4 before recording. Therefore, by reducing the resistance value of the memory thin film 4, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc., but in the erasing process, for example, an ion source layer 3 containing Cu, Ag, Zn is formed on the ion source layer 3. A negative potential (−potential) is applied, and a negative voltage is applied to the memory element 10 so that the upper electrode 6 side becomes positive. As a result, Cu, Ag, and Zn constituting the current path or impurity level formed in the memory thin film 4 are ionized, move in the memory thin film 4, and return to the ion source layer 3 side.
Then, the current path or defect due to Cu, Ag, Zn disappears from the memory thin film 4, and the resistance value of the memory thin film 4 increases. Since each layer other than the memory thin film 4 originally has a low resistance value, the resistance value of the memory element 10 as a whole can be increased by increasing the resistance value of the memory thin film 4.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

In particular, the ion source layer 3 contains an element selected from Te, S, Se, that is, a chalcogen element in addition to the above-described metal elements (Cu, Ag, Zn), so that the metal element in the ion source layer 3 is obtained. (Cu, Ag, Zn) and a chalcogen element (Te, S, Se) are combined to form a metal chalcogenide layer. The metal chalcogenide layer mainly has an amorphous structure. For example, when a positive potential is applied to the side of the lower electrode 2 in contact with the ion source layer 3 made of the metal chalcogenide layer, the metal element contained in the metal chalcogenide layer (Cu, Ag, Zn) is ionized and diffused into the memory thin film 4 exhibiting high resistance, and is combined with the electrons and deposited on a part of the upper electrode 6 side, or in the memory thin film 4 By forming the impurity level of the insulating film, the resistance of the memory thin film 4 is lowered, and information can be recorded.
From this state, when a negative potential is applied to the lower electrode 2 side in contact with the ion source layer 3 made of a metal chalcogenide layer, the metal elements (Cu, Ag, Zn) deposited on the upper electrode 6 side are ionized again, By returning to the metal chalcogenide layer, the resistance of the memory thin film 4 returns to the original high state, and the resistance of the memory element 10 is also increased, so that the recorded information can be erased.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

The memory thin film 4 generally has a high resistance in the initial state before recording. However, the memory thin film 4 exhibits a low resistance in the initial recording state by plasma treatment, annealing treatment, or the like in the process step. It doesn't matter.
The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the memory thin film 4, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio of the initial resistance value to the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance after recording is It is sufficient if the value is 50Ω, or the resistance value before recording is 100 kΩ, and the resistance value after recording is 50 kΩ, and the initial resistance value of the memory thin film 4 is set to satisfy such a condition. The The resistance value of the memory thin film 4 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials.

  According to the configuration of the memory element 10 of the above-described embodiment, by adopting a configuration in which the ion source layer 3 and the memory thin film 4 are sandwiched between the lower electrode 2 and the upper electrode 6, for example, When a positive voltage (+ potential) is applied to the ion source layer 3 side so that the upper electrode 6 side becomes negative, a current path containing a large amount of Cu, Ag, and Zn is formed in the memory thin film 4. In addition, by forming a large number of defects due to Cu, Ag, and Zn in the memory thin film 4, the resistance value of the memory thin film 4 is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored by utilizing a change in the resistance value of the memory element 10, in particular, a change in the resistance value of the memory thin film 4, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

  Further, for example, when used in a storage device that can be erased in addition to recording such as RAM and EEPROM, for example, a negative voltage ( -Potential) is applied so that the upper electrode 6 side becomes positive. As a result, the current path or defect due to Cu, Ag, Zn formed in the memory thin film 4 disappears, the resistance value of the memory thin film 4 increases, and the resistance value of the entire memory element 10 increases. Become. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

In addition, according to the memory element 10 of the present embodiment, the ion source layer 3 can be made non-uniform by making the ion source layer 3 contain boron B or by making the ion source layer 3 contain rare earth elements and silicon Si. A crystalline structure or a uniform microcrystalline structure with a very small particle size can be obtained.
With such a structure, even if heat is applied to the memory element 10 in a heat treatment process or the like, the fine structure of the ion source layer 3 is kept stable, and the film state (surface state, etc.) of the ion source layer 3 is good. Is maintained in a stable state. That is, the fine structure of the ion source layer 3 can be kept stable even in a high temperature heat treatment process required in a semiconductor process, particularly in a wiring process.
Then, by maintaining the film state (surface state, etc.) of the ion source layer 3 in a good state, the distribution of the electric field applied to the memory thin film 4 becomes uniform, and the memory element 10 is changed from the high resistance state to the low resistance state. Since the threshold value (switching voltage) of the voltage at the time of changing to a state can be reduced, a uniform value can be obtained even if recording / erasing is repeated.
That is, even after the high temperature heat treatment is performed, the ion source layer 3 and the memory thin film (memory layer) 4 can be kept in a good state, and the heat resistance of the memory element 10 can be improved.

Further, according to the memory element 10 of the present embodiment, the lower electrode 2, the ion source layer 3, the memory thin film 4, and the upper electrode 6 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

In the memory element 10 of the above-described embodiment, when the memory thin film 4 has a configuration in which a film made of an oxide of a rare earth element (rare earth oxide thin film) is formed in a part thereof, the oxide thin film It is formed by using a method using a sputtering target of an oxide, a method using a metal target, introducing oxygen together with an inert gas such as argon during sputtering, a method such as so-called reactive sputtering. Is possible.
Furthermore, in addition to sputtering, an oxide thin film can be formed by a method such as CVD or vapor deposition. In addition, the film is in a metal state at the time of film formation, and thereafter a method such as thermal oxidation or chemical treatment. It is also possible to form an oxide thin film.

The memory element 10 of FIG. 1 can be manufactured as follows, for example.
First, a lower electrode 2, for example, a TaN film is deposited on a substrate 1 having high electrical conductivity, for example, a silicon substrate doped with a high concentration of P-type impurities.

Next, an ion source layer 3, for example, a CuTeGeBSiGd film is formed, and then a memory thin film 4, for example, a Gd ₂ O ₃ film is formed.

  Thereafter, the insulating layer 5 is formed so as to cover the memory thin film 4, but a part of the insulating layer 5 is removed by photolithography to form a contact portion to the memory thin film 4.

Subsequently, for example, a W film is formed as the upper electrode 6 by, for example, a magnetron sputtering apparatus.
Thereafter, the W film is patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
In this way, the memory element 10 shown in FIG. 1 can be manufactured.

By using the memory element 10 of the above-described embodiment and arranging a large number of memory elements 10 in, for example, a column shape or a matrix shape, a memory device (memory) can be configured.
For each memory element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 6 side are provided. For example, each memory element 10 is arranged near the intersection of these wirings. What should I do?

  Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the upper electrode 6 is formed in common in the memory cell in the column direction, and a current is applied by applying a potential. By selecting the lower electrode 2 and the wiring to be flown, a memory cell to be recorded is selected, and a current is passed through the memory element 10 of this memory cell to record information or erase the recorded information. it can.

The storage element 10 according to the above-described embodiment can easily and stably record information and read information, and has particularly excellent characteristics in high temperature environment and long-term data retention stability. .
Further, even when the memory element 10 according to the above-described embodiment is miniaturized, it becomes easy to record information and hold the recorded information.
Therefore, by configuring the storage device using the storage element 10 of the above-described embodiment, the storage device can be integrated (high density) or downsized.

(Example)
Next, a laminated film of the memory element according to the present invention was produced and the characteristics thereof were examined.

(Structural analysis by X-ray diffraction)
On the silicon wafer as the substrate, the lower electrode, the ion source layer, and the memory thin film were formed to form a laminated film constituting the memory element.
First, a TaN film with a thickness of 20 nm as a lower electrode, a Cu ₅₃ Te ₂₈ Ge ₁₂ Gd ₇ film with a thickness of 20 nm as an ion source layer (numbers are atomic%), and a Gd ₂ O ₃ film with a thickness of 2.4 nm as a memory thin film. To form a laminated film of Sample 1.
Next, a TaN film with a thickness of 20 nm as a lower electrode, a Cu ₄₄ Te ₂₅ Ge ₆ Gd ₆ Si ₁₄ B ₅ film with a thickness of 20 nm as an ion source layer (numbers are atomic%), and a film thickness of 2.4 nm as a memory thin film. Each of Gd ₂ O ₃ was formed as a laminated film of Sample 2.
Next, a 20 nm thick TaN film is formed as the lower electrode, a 20 nm thick Cu ₄₅ Te ₂₇ Ge ₇ Gd ₆ Si ₁₅ film is formed as the ion source layer, and a 2.4 nm thick Gd ₂ O ₃ film is formed as the memory thin film. Thus, a laminated film of Sample 3 was obtained.
Next, a 20 nm thick TaN film as the lower electrode, a 20 nm thick Cu ₄₅ Te ₂₇ Ge ₇ Si ₁₅ B ₆ film (number is atomic%) as the ion source layer, and a 2.4 nm thick Gd as the memory thin film. ₂ O ₃ was formed to form a laminated film of Sample 4.
Next, TaN film having a thickness 20nm as the lower electrode, the ion source layer as the thickness 20nm of _{Cu 42 Te 24 Ge 6 Gd 6} Si 14 B 8 film (numeral atomic%), the film thickness as the memory thin 2.4nm Each of Gd ₂ O ₃ was formed as a laminated film of Sample 5.
These laminated film samples are not patterned in a state where the laminated film is formed.
Among these samples, Sample 2 to Sample 5 are configurations (examples) of the memory element of the present invention, and Sample 1 is a configuration of a comparative example for the present invention.

Next, with respect to the laminated film of Sample 1, immediately after the film formation and after the memory thin film was formed, the film was evacuated and then replaced with a nitrogen atmosphere, and heat treatment was performed in a nitrogen atmosphere at 280 ° C. for 1 hour. Thereafter, the X-ray diffraction intensity was measured using an X-ray diffractometer, and the surface roughness Ra of the film was measured using an AFM (Atomic Force Microscope).
The measurement result of X-ray diffraction is shown in FIG.

From FIG. 2, it can be seen that a peak at a specific angle does not appear immediately after the film formation, but a peak is observed after the heat treatment, and the fine structure of the film is changed by crystallization.
Further, the surface roughness Ra of the film is 0.23 nm immediately after the film formation, and is as large as 0.35 nm after the heat treatment. It is considered that the structure locally changed and the fine surface shape changed accordingly.
As comparative reference data, the surface roughness Ra of the silicon wafer surface having a natural oxide film formed on the surface was measured and found to be 0.14 nm.

Next, with respect to the laminated film of sample 2, the sample (2A) immediately after film formation and the sample (2B) subjected to heat treatment in a nitrogen atmosphere at 400 ° C. for 1 hour after being immersed in TMAH (tetramethylammonium hydroxide aqueous solution) And a sample (2C) that was heat-treated in a nitrogen atmosphere at 400 ° C. for 1 hour without chemical treatment, and for each sample, the X-ray diffraction intensity was measured using an X-ray diffractometer, The surface roughness Ra of the film was measured using AFM.
The measurement results are shown in FIG. In FIG. 3, the sample name (2A to 2C) and the measured value of the surface roughness Ra are shown on the right side of the X-ray diffraction intensity.

As shown in FIG. 3, the sample 2C subjected to the heat treatment in a nitrogen atmosphere at 400 ° C. does not show an X-ray diffraction peak even though the heat treatment temperature is higher than that of the sample 1 in FIG. It can be seen that Also for the surface roughness Ra, a very good value comparable to that of the sample 2A immediately after film formation is obtained.
Thereby, for example, even when the element size is miniaturized to about 50 nm or less, it is expected that the problem of deterioration of characteristics due to change of the film microstructure does not occur.
Further, in the sample 2B subjected to the chemical treatment, the surface roughness Ra is improved as compared with the sample 2A immediately after the film formation. For example, the surface property can be improved by performing the heat treatment after performing the oxidation / reduction reaction with the chemical. It is possible to improve.

Next, for the laminated films of Sample 3 to Sample 5, samples that were heat-treated in a nitrogen atmosphere at 400 ° C. for 1 hour were prepared, and the X-ray diffraction intensity was measured using an X-ray diffractometer, respectively. The surface roughness Ra of the film was measured.
The measurement results are shown in FIG. In FIG. 4, sample numbers (No. 3 to No. 5) and measured values of the surface roughness Ra are shown on the right side of the X-ray diffraction intensity.

From FIG. 4, it can be seen that sample 3 can suppress the promotion of crystallization after high-temperature heat treatment by adding rare earth elements, silicon, and boron B to the ion source layer containing CuTe as the main component.
Sample 4 shows an X-ray diffraction peak, but considering the high heat treatment temperature of 400 ° C. and the value of surface roughness Ra, the high temperature stability is improved as compared with sample 1 shown in FIG. You can see that
Sample 5 also shows a broad X-ray diffraction peak, which is due to the microcrystals of boron, and the surface roughness Ra after heat treatment is very good. There seems to be no problem.

(Observation of the cross-sectional structure of the film with a transmission electron microscope)
On the silicon substrate on which a natural oxide film was formed as a substrate, the lower electrode, the ion source layer, and the memory thin film were formed to form a laminated film constituting the memory element.
First, a WN film having a thickness of 20 nm is formed as a lower electrode, a Cu ₅₄ Te ₃₂ Ge ₈ Gd ₆ film (number is atomic%) is formed as an ion source layer, and a GdN film having a thickness of 2.8 nm is formed as a memory thin film. A laminated film of Sample 6 was obtained.
Next, a WN film having a thickness of 20 nm is formed as a lower electrode, a Cu ₄₅ Te ₂₇ Ge ₇ Gd ₆ B ₁₆ film (number is atomic%) is formed as an ion source layer, and a GdN film having a thickness of 2.8 nm is formed as a memory thin film. Thus, a laminated film of Sample 7 was obtained.
Next, a WN film having a thickness of 20 nm is formed as a lower electrode, a Cu ₃₉ Te ₂₃ Ge ₆ Gd ₅ Si ₁₆ B ₁₃ film is formed as an ion source layer, and a GdN film having a thickness of 2.8 nm is formed as a memory thin film. 8 laminated film.
These laminated film samples are not patterned in a state where the laminated film is formed. The film thickness of the ion source layer was set in the range of 25 nm to 30 nm.
Among these samples, Sample 7 and Sample 8 are configurations (examples) of the memory element of the present invention, and Sample 6 is a configuration of a comparative example for the present invention.
The laminated films of Sample 6 to Sample 8 were subjected to heat treatment in a nitrogen atmosphere at 280 ° C. for 1 hour, and then each of the laminated films was observed using a transmission electron microscope and electron diffraction was performed. Got a pattern.
The obtained electron diffraction patterns are shown in FIGS. 5A to 5C. 5A shows the electron diffraction pattern of each laminated film of Sample 6, FIG. 5B shows Sample 7, and FIG.

Sample 6 was found from the observation result of the cross section and the electron diffraction pattern of FIG. 5A that the ion source layer was crystallized and the local microstructure was not uniform.
On the other hand, the sample 7 to which boron B is added has a uniform fine structure based on the observation result of the cross section and the electron diffraction pattern of FIG. 5B, and the electron diffraction pattern is a concentric pattern peculiar to the amorphous structure. I understood it. Sample 8 was the same as sample 7.

  Next, the memory element 10 of the above-described embodiment was actually manufactured, and its characteristics were examined.

<Experiment 1>
On the silicon substrate, a WN film is deposited as a lower electrode 2 to a thickness of 20 nm, a Cu ₆₁ Te ₂₁ Ge ₅ B ₈ film is formed thereon as an ion source layer 3, and a GdN film is formed as a memory thin film 4. A film was formed with a thickness of .5 nm, and a photoresist was formed to cover the surface. Thereafter, exposure and development were performed by a photolithography technique to form an opening (through hole) in the photoresist on the memory thin film 4.
After that, after evacuating to a vacuum, the atmosphere is replaced with a nitrogen atmosphere, annealing is performed in the nitrogen atmosphere, the photoresist is altered, and the insulating layer 5 is formed as a hard cure resist that is stable with respect to temperature and etching. did. The hard-cure resist is used for the insulating layer 5 because it can be easily formed experimentally. In the case of manufacturing a product, another material (for example, a silicon oxide film) is used for the insulating layer 5. Better.
Next, a W film having a thickness of 90 nm was formed as the upper electrode 6. Thereafter, the upper electrode 6 deposited on the insulating layer 5 made of a hard-cure resist was patterned by a photolithography technique using a plasma etching apparatus. Further, the laminated films 2, 3, and 4 of the memory element 10 were patterned into a circular shape having a diameter of 0.7 μm.
The memory element 10 having such a structure was manufactured and used as a sample memory element of Sample 9.

Further, a Cu ₅₃ Te ₂₁ Ge ₅ B ₂₀ film was formed as the ion source layer 3, and a memory element 10 was produced in the same manner as in the sample 9 except that the memory element of the sample 10 was obtained.

Each of the memory elements of Sample 9 and Sample 10 was subjected to a heat treatment in a nitrogen atmosphere at 280 ° C., and then the IV characteristics were measured.
The IV measurement was performed as follows.
For the memory element of each sample, the back surface of the low-resistance silicon substrate 1 electrically connected to the lower electrode 2 was connected to the ground potential (ground potential), and a negative potential (−potential) was applied to the upper electrode 6.
Then, the negative potential applied to the upper electrode 6 was decreased from 0 V, and the change in current was measured. However, the current limiter is set to operate when the current reaches 1 mA, and beyond that, the negative potential applied to the upper electrode 6, that is, the absolute value of the voltage applied to the memory element is not increased. did.
Further, from the state where the current reached 1 mA and the current limiter was operated, the negative potential applied to the upper electrode 6 was decreased to 0 V, and the change in current was measured. Subsequently, this time, a positive potential was applied to the upper electrode 6, and the operation of returning the potential to 0 potential again was performed after increasing the application of the positive voltage to such a voltage that the current decreased and no current flowed.
The measurement results of the IV characteristics obtained in this way are shown in FIGS. 6A and 6B. 6A shows the measurement result of the sample 9, and FIG. 6B shows the measurement result of the sample 10. FIG.

6A and 6B, the resistance value is initially high, the memory element is in the OFF state, and the voltage increases in the negative direction, so that the current increases rapidly at a certain threshold voltage (Vth) or higher. That is, it can be seen that the resistance value decreases and the memory element transitions to the ON state. Thereby, it is understood that information is recorded.
On the other hand, even if the voltage is decreased thereafter, a constant resistance value is maintained. That is, it can be seen that the storage element is kept in the ON state and the recorded information is held.
Further, a voltage V having a polarity opposite to that described above, that is, the back side of the substrate 1 is connected to a ground potential (ground potential), and a positive potential (+ potential) of V = 0.2 V or more is applied to the upper electrode 6. Then, it was confirmed that the resistance value of the memory element returned to the initial high resistance state in the OFF state by returning to 0 V again. That is, it can be seen that the information recorded in the memory element can be erased by applying a negative voltage.
That is, it was found that information can be recorded and erased satisfactorily.

<Experiment 2>
A Cu ₆₁ Te ₂₇ Ge ₇ Gd ₅ film was formed as the ion source layer 3, and a memory element 10 was produced in the same manner as in the sample 9 except that the memory element of the sample 11 was obtained.
In addition, a Cu ₅₆ Te ₂₅ Ge ₆ Gd ₅ B ₈ film was formed as the ion source layer 3, and a memory element 10 was fabricated in the same manner as in the sample 9 except that the memory element of the sample 12 was obtained.
In addition, a Cu ₅₁ Te ₂₃ Ge ₆ Gd ₅ B ₁₅ film was formed as the ion source layer 3, and the memory element 10 was produced in the same manner as in the sample 9, and a sample 13 sample memory element was obtained.
Further, a Cu ₄₉ Te ₂₁ Ge ₅ Gd ₄ B ₂₀ film was formed as the ion source layer 3, and the memory element 10 was produced in the same manner as in the sample 9 except that the memory element of the sample 14 was obtained.
Among these samples, sample 12 to sample 14 are configurations (examples) of the memory element of the present invention, and sample 11 is a configuration of a comparative example for the present invention.

  Each of the memory elements of Samples 11 to 14 was subjected to heat treatment in a nitrogen atmosphere at 350 ° C., and then each sample was subjected to I− of the memory elements of three different cells produced in the same wafer. V characteristics were measured, and variations in IV characteristics were examined. The measurement results of the sample 11 are shown in FIGS. 7A to 7C, the measurement results of the sample 12 are shown in FIGS. 8A to 8C, the measurement results of the sample 13 are shown in FIGS. 9A to 9C, and the measurement results of the sample 14 are shown in FIG. -Shown in FIG. 10C.

  From FIG. 7A to FIG. 7C, it can be seen that in the sample 11 which is a comparative example, the IV characteristics vary in three cells of the same wafer even though the film forming conditions are the same. In particular, in the cell shown in FIG. 7A, a current of 0.35 mA or more flows in the erased state. This is because the fine film structure is changed by heat treatment in a nitrogen atmosphere at 350 ° C., and the memory thin film (memory layer). This is thought to be due to the fact that the effective film thickness has become thinner due to changes in the structure.

On the other hand, it can be seen from FIGS. 8A to 10C that Sample 12 to Sample 14 which are examples of the present invention have small variations in IV characteristics for each cell, and stable characteristics can be obtained.
7 to 10 are compared in order, it can be seen that the current in the erased state decreases as the boron B content increases. By adding boron, the fine structure of the ion source layer It is presumed that the thermal stability of is improved.

<Experiment 3>
A memory element having a configuration in which the ion source layer 3 contains a rare earth element and silicon Si was manufactured, and IV characteristics were examined.
A Cu ₅₁ Te ₃₁ Ge ₈ Gd ₆ Si ₄ film was formed as the ion source layer 3, and a memory element 10 was produced in the same manner as in the sample 9 except that the memory element of the sample 15 was obtained.
In addition, a Cu ₄₈ Te ₂₈ Ge ₇ Gd ₆ Si ₁₂ film was formed as the ion source layer 3, and the memory element 10 was fabricated in the same manner as in the sample 9, and a sample 16 sample memory element was obtained.
Further, a Cu ₄₀ Te ₂₄ Ge ₆ Gd ₅ Si ₂₆ film was formed as the ion source layer 3, and the memory element 10 was produced in the same manner as the sample 9 except that it was used as the sample memory element of the sample 17.

  The memory elements of Samples 15 to 17 were each subjected to heat treatment in a nitrogen atmosphere at 280 ° C., and then the IV characteristics were measured. The measurement results of the IV characteristics are shown in FIGS. 11A to 11C. 11A shows the measurement result of the sample 15, FIG. 11B shows the measurement result of the sample 16, and FIG. 11C shows the measurement result of the sample 17.

  11A to 11C, in Samples 15 to 17 in which the rare earth element and silicon are contained in the ion source layer, the memory element after the heat treatment is also excellent in the same manner as the sample in which boron is contained in the ion source layer. It can be seen that the -V characteristic is maintained.

<Experiment 4>
A memory element having a configuration in which the ion source layer 3 contains boron B, a rare earth element, and silicon Si was manufactured, and IV characteristics were examined.
A Cu ₄₄ Te ₂₆ Ge ₇ Gd ₅ B ₈ Si ₁₁ film was formed as the ion source layer 3, and the memory element 10 was fabricated in the same manner as in the sample 9 except that the memory element of the sample 18 was obtained.
Further, a Cu ₄₁ Te ₂₅ Ge ₆ Gd ₅ B ₁₃ Si ₁₀ film was formed as the ion source layer 3, and the memory element 10 was produced in the same manner as in the sample 9, and a memory element of the sample 19 was obtained.
In addition, a Cu ₃₉ Te ₂₃ Ge ₆ Gd ₅ B ₁₈ Si ₁₀ film was formed as the ion source layer 3, and the memory element 10 was produced in the same manner as in the sample 9 to obtain a sample memory element of the sample 20.

  Each of the memory elements of Samples 18 to 20 was subjected to heat treatment in a nitrogen atmosphere at 280 ° C., and then the IV characteristics were measured. The measurement results of the IV characteristics are shown in FIGS. 12A to 12C. 12A shows the measurement result of the sample 18, FIG. 12B shows the measurement result of the sample 19, and FIG. 12C shows the measurement result of the sample 20.

  12A to 12C, samples 18 to 20 in which boron, a rare earth element, and silicon are included in the ion source layer are also included in the sample in which boron is included in the ion source layer, and the rare earth element and silicon are included in the ion source layer. It can be seen that the memory element after heat treatment maintains good IV characteristics as in the case of the contained sample.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. It is possible to apply any memory form such as (memory).

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of the memory element of one embodiment of this invention. It is the measurement result of the X-ray diffraction immediately after film-forming of the laminated film of the sample 1, and after heat processing. It is the measurement result of the X-ray diffraction of the three samples from which the processing conditions of the laminated film of the sample 2 differ, and the measured value of surface roughness. It is the measurement result of the X-ray diffraction of the laminated film of Sample 3 to Sample 5, and the measured value of the surface roughness. A is an electron diffraction pattern of the laminated film of Sample 6. B is an electron diffraction pattern of the laminated film of Sample 7. C is an electron diffraction pattern of a laminated film of Sample 8. A is a measurement result of IV characteristics of the memory element of Sample 9. B is a measurement result of IV characteristics of the memory element of sample 10. A to C are measurement results of IV characteristics of the memory elements of the three cells of the sample 11. A to C are measurement results of IV characteristics of the memory elements of the three cells of the sample 12. A to C are measurement results of IV characteristics of the memory elements of the three cells of the sample 13. A to C are measurement results of IV characteristics of the memory elements of the three cells of the sample 14. A is a measurement result of IV characteristics of the memory element of Sample 15. B is a measurement result of IV characteristics of the memory element of sample 16. C is a measurement result of IV characteristics of the memory element of sample 17. A is a measurement result of IV characteristics of the memory element of Sample 18. B is a measurement result of IV characteristics of the memory element of sample 19. C is a measurement result of IV characteristics of the memory element of sample 20.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower electrode, 3 Ion source layer, 4 Memory thin film (memory layer), 5 Insulating layer, 6 Upper electrode, 10 Memory element

Claims (6)

A storage layer and an ion source layer are sandwiched between the first electrode and the second electrode,
A storage element, wherein the ion source layer contains Cu, Te, and boron. The memory element according to claim 1, wherein the ion source layer further contains a rare earth element or silicon. A storage layer and an ion source layer are sandwiched between the first electrode and the second electrode,
A storage element, wherein the ion source layer contains Cu, Te, a rare earth element, and silicon. A memory element including a memory layer and an ion source layer sandwiched between the first electrode and the second electrode, wherein the ion source layer contains Cu, Te, and boron;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device in which a large number of the storage elements are arranged . The storage device according to claim 4, wherein the ion source layer of the storage element further contains a rare earth element or silicon. Between the first electrode and the second electrode, the storage layer and the ion source layer is configured sandwiched, in the ion source layer, and a memory element Cu and Te and the rare earth element and silicon is contained,
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device in which a large number of the storage elements are arranged .