JP5103932B2 - Storage element and storage device - Google Patents

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, flash memories, FeRAMs (ferroelectric memories), MRAMs (magnetic storage elements), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.
Accordingly, extensive research and product development have been conducted on the various types of nonvolatile memories described above.

However, the various nonvolatile memories described above have advantages and disadvantages.
Flash memory has a high degree of integration, but is disadvantageous in terms of operation speed.
FeRAM has a limit in microfabrication for high integration and has a problem in a manufacturing process.
MRAM has a problem of power consumption.

Therefore, a new type of storage element has been proposed that is particularly advantageous for the limit of microfabrication of the memory element.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. By diffusing, electrical characteristics such as resistance value or capacitance of the ionic conductor change.
A memory device can be configured using this characteristic (see, for example, Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and a metal, and more specifically, made of a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Ag, Cu, and Zn (see Patent Document 1).

Special Table 2002-536840 Publication

In the structure of the memory element described above, when information is recorded on the memory element and then left for a long time or when left in a temperature atmosphere higher than room temperature, the resistance value of the memory element changes and is recorded. There is a problem that it becomes impossible to hold the information.
Thus, when the information retention capability is low, the element characteristics used in the nonvolatile memory are insufficient.

  In addition, in a so-called “write” operation that transitions from a high-resistance state to a low-resistance state, and a so-called “erase” operation that transitions from a low-resistance state to a high-resistance state, it is desirable that the current value flowing through the memory element is small. This is advantageous in reducing power.

By the way, when a write / erase operation is performed with a relatively large current, a write / erase operation can be performed at a lower current with respect to a memory element having the same configuration (material / dimension) even if excellent information retention characteristics are obtained. If this is done, sufficient information retention characteristics may not be obtained. In general, the information retention characteristics decrease as the drive current decreases.
If a transistor with a large area and a large driving capability is used as a transistor for driving the memory element, a large current can flow through the memory element. However, if a transistor with a small area and a small driving capability is used, a current that can be passed through the memory element. The amount becomes smaller.
In order to reduce the memory circuit in order to increase the density of the memory, it is necessary to reduce the size of the transistor for driving the memory element, so that the current driving capability of the transistor is also lowered.

  Therefore, in order to increase the density of the memory, it is required to obtain necessary information retention characteristics even when the memory element is operated at a lower current.

  In order to solve the problems and problems described above, the present invention provides a memory element that can retain information even when a write / erase operation is performed at a low current, and a memory device using the memory element. is there.

The memory element of the present invention is configured by sandwiching a memory layer between a first electrode and a second electrode, and the memory layer is sufficiently more than the ionized layer containing Cu to be ionized and the ionized layer. It consists of a high resistance layer having a high resistance value, and the ionization layer is a CuTeSi film, and in the ionization layer, the composition ratio of Cu content (atomic%) / Te content (atomic%) is 1 or more and 3 or less. The Si content (atomic%) in the layer is 10% or more and 45% or less , and the high resistance layer is made of an oxide containing one or more elements selected from rare earth elements, Si, and Cu .
A memory device of the present invention includes the memory element of the present invention, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. Is.

  According to the configuration of the memory element of the present invention described above, the memory layer is configured to be sandwiched between the first electrode and the second electrode, and the memory layer includes an ionized layer containing Cu to be ionized, By comprising a high resistance layer having a resistance value sufficiently higher than that of the ionized layer, information can be stored by utilizing the change in the resistance state of the high resistance layer included in the memory layer.

Specifically, for example, when a positive potential is applied to one electrode on the ionization layer side containing Cu and a positive voltage is applied to the memory element, Cu contained in the ionization layer is ionized to be in the high resistance layer. The resistance value of the high-resistance layer is lowered by diffusing to and depositing by combining with electrons at the other electrode side, or by forming impurity levels in the insulating film that remain in the high-resistance layer. Since the resistance value of the memory layer including the high resistance layer is lowered, information can be written.
Also, from this state, when a negative potential is applied to one electrode on the ionization layer side and a negative voltage is applied to the memory element, Cu deposited on the other electrode side is ionized again, and is applied to one electrode side. By returning, the resistance value of the storage layer returns to the original high state, and the resistance value of the storage element also increases, so that the recorded information can be erased.

And since a memory layer has a high resistance layer whose resistance value is sufficiently higher than that of an ionized layer, the resistance value of the memory layer in a high resistance state can be made relatively high.
Moreover, the ionization layer is a CuTeSi film, and by containing Te (chalcogenide element) , ionization of Cu is promoted.
Furthermore, when the ionized layer contains Si, the mobility of Cu ions can be reduced, the thermal activation energy can be reduced, and the thermal diffusion of Cu can be suppressed. Accordingly, Cu atoms are less likely to move unless a voltage is applied to the memory element while Cu is maintained in a low resistance state or a high resistance state. For this reason, the resistance state of the memory layer can be stably maintained, and the information retention characteristics can be improved.
Furthermore, in the ionized layer, the composition ratio of Cu content (atomic%) / Te content (atomic%) is 1 or more and 3 or less, so that information can be recorded and erased correctly without causing film peeling. It can be carried out. Further, when the content (atomic%) of Si in the ionized layer is 10% or more and 45% or less, sufficient information retention characteristics can be obtained.

  According to the configuration of the memory device of the present invention described above, the memory element of the present invention, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, By arranging a large number, the current can be passed from the wiring to the storage element, and information can be recorded or erased.

According to the above-described present invention, the resistance state of the memory layer of the memory element can be stably held, and the information retention characteristics can be improved. Therefore, even if the write / erase operation is performed with a low current, the information It becomes possible to hold.
By performing the write / erase operation with a low current, the power consumption during the operation can be reduced.
In addition, since writing / erasing operations can be performed with low current, the size of a selection transistor for driving a memory element can be reduced and a memory cell of the memory device can be miniaturized. .

Therefore, according to the present invention, a storage device (memory) that operates stably and consumes less power can be realized.
In addition, since the memory cell of the storage device (memory) can be miniaturized, the storage device can be reduced in size, increased in density, and increased in storage capacity.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element 10 is shown in FIG.
In the memory element 10, for example, a lower electrode 1, which is a connection portion with a CMOS circuit portion, is formed on a silicon substrate (see FIG. 2) on which a CMOS circuit is formed, and a memory layer is formed on the lower electrode 1. 5 is formed, and the upper electrode 4 is formed on the memory layer 5.

  The memory layer 5 is composed of a stack of a high resistance layer 2 made of, for example, an oxide and an ionized layer 3 containing copper Cu that becomes ions.

For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.
In addition, when using an electrode material that may cause ion conduction in an electric field such as Cu, it is used by covering the Cu electrode with a material that is difficult to ionize or thermally diffuse such as W, WN, TiN, or TaN. Also good.

The ionization layer 3 constituting the memory layer 5 is configured to contain an element (chalcogenide element) selected from Te, Se, and S in addition to copper Cu. For such an ionized layer 3, for example, CuTeSi, CuSSi, or CuSeSi can be used.
Further, as a method of forming such an ionized layer 3, in addition to a method of forming a film having the composition, an alloy film not containing Cu (such as TeSi) is formed, and then a desired composition is obtained. A method of forming a Cu film later to form a laminated film and diffusing and mixing each element by heat treatment or the like is also conceivable.

  The ionized layer 3 preferably has a thickness of 5 nm or more.

The high resistance layer 2 constituting the memory layer 5 has a sufficiently higher resistance value than the ionization layer 3.
For the high resistance layer 2, an oxide, a nitride, or the like can be used.
More preferably, the high resistance layer 2 includes one or more elements selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y among rare earth elements, An oxide containing Si and Cu is used.

  As with the lower electrode 1, a normal semiconductor wiring material is used for the upper electrode 4.

  The memory layer 5 (2, 3) having the above-described configuration has a characteristic that impedance changes when a voltage pulse or a current pulse is applied.

The storage element 10 of this embodiment can be operated as follows to store information.
First, for example, a positive potential (+ potential) is applied to the upper electrode 4, and a positive voltage is applied to the memory element 10 so that the lower electrode 1 side becomes negative. As a result, Cu ions are ion-conducted from the ionized layer 3, are combined with electrons on the lower electrode 1 side, and are deposited, and a Cu current path is formed in the high-resistance layer 2. The value becomes lower. Each of the layers other than the high resistance layer 2 originally has a lower resistance value than the resistance value of the high resistance layer 2, so that the resistance value of the entire memory element 10 is also lowered by lowering the resistance value of the high resistance layer 2. be able to.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc. In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 4, A negative voltage is applied to the memory element 10 so that the lower electrode 1 side is positive. Thereby, Cu in the current path formed in the high resistance layer 2 is oxidized and ionized, and dissolved in the ionized layer 3 or combined with Te to form a compound such as Cu ₂ Te or CuTe.

  Then, the current path due to Cu disappears or decreases from within the high resistance layer 2, and the resistance value of the high resistance layer 2 increases. Since each layer other than the high resistance layer 2 originally has a low resistance value, the resistance value of the entire memory element 10 can be increased by increasing the resistance value of the high resistance layer 2.

  After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

The resistance value after recording depends on the recording conditions such as the width and current amount of the voltage pulse or current pulse applied during recording, rather than the cell size of the memory element 10 and the material composition of the high resistance layer 2, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio of the initial resistance value to the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance after recording is It is sufficient if the value is 50Ω, or the resistance value before recording is 100 kΩ and the resistance value after recording is 50 kΩ, and the initial resistance value of the high resistance layer 2 is set to satisfy such a condition. The
The resistance value of the high resistance layer 2 can be controlled by, for example, the amount of oxygen contained in the rare earth element, Cu, Si oxide of the high resistance layer 2 before heat treatment, the oxide film thickness, and the like.

  According to the configuration of the memory element 10 described above, the high resistance layer 2 and the ionized layer 3 containing Cu are sandwiched between the lower electrode 1 and the upper electrode 4. 4, when a positive voltage (+ potential) is applied so that the lower electrode 1 side becomes negative, a current path containing a large amount of Cu is formed in the high resistance layer 2, and the high resistance layer 2 The resistance value is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

Further, for example, when used in a storage device that can be erased in addition to recording such as RAM and EEPROM, a negative voltage (−potential) is applied to the upper electrode 4 with respect to the storage element 10 in the state after recording described above. Is applied so that the lower electrode 1 side becomes positive.
As a result, the Cu current path formed in the high resistance layer 2 disappears, the resistance value of the high resistance layer 2 increases, and the resistance value of the entire memory element 10 increases. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

A memory device (memory device) can be configured by arranging a large number of memory elements 10 having the above-described configuration in a matrix.
For each memory element 10, a wiring connected to the lower electrode 1 side and a wiring connected to the upper electrode 4 side are provided. For example, each memory element 10 is disposed near the intersection of these wirings. What should I do?

Further, for example, it is conceivable to form a memory device by forming wirings connected to the upper electrode 4 in common for the entire memory cell array.
FIG. 2 and FIG. 3 show schematic configuration diagrams of an embodiment of the memory cell array configured as described above. 2 is a cross-sectional view, and FIG. 3 is a plan view.

  As shown in FIGS. 2 and 3, in this memory cell array, the memory element 10 constituting each memory cell shares the layers of the high resistance layer 2, the ionized layer 3, and the upper electrode 4 over the entire memory cell. . In other words, each memory element 10 is composed of the same high resistance layer 2, ionized layer 3, and upper electrode 4.

The upper electrode 4 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. A memory element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 2, each storage element 10 constituting each memory cell of the memory cell array is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element 10.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the memory element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. The metal wiring layer 16 is connected to the bit line BL (see FIG. 3) which is the other address wiring of the memory element 10.

  In FIG. 3, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 3, reference numeral 21 denotes a contact portion that communicates with the lower electrode 1 of the memory element 10, and 22 denotes a contact portion that communicates with the bit line BL.

The memory cell array shown in FIGS. 2 and 3 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.
Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 4 (plate electrode PL), the resistance value of the memory element 10 transitions to a low resistance state. To do. Thereby, information can be recorded in the memory element 10 of the selected memory cell.
Further, by applying a voltage having a positive potential to the lower electrode 1 as compared with the potential of the upper electrode 4 (plate electrode PL), the resistance value of the memory element 10 transitions to the high resistance state again. Thereby, the recorded information can be erased from the storage element 10 of the selected memory cell.

In order to read out recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the memory element 10 is changed. Different currents or voltages are detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the memory element 10 changes.

  By the way, a resistance holding characteristic of the resistance value in the low resistance state after applying the voltage to the memory element 10 and performing the writing operation and the resistance value in the high resistance state after performing the erasing operation. Depends on the composition ratio between Cu, which is an ionizing element, and a chalcogenide element (for example, Te), and the type and composition ratio of the matrix element.

For example, when the composition ratio of Cu / Te is smaller than 1, a CuTe compound is easily formed, and when Cu is ionized, it is likely to exist in a divalent Cu ²⁺ state.
Since the divalent Cu ²⁺ is considered to be strongly bound to the chalcogenide anion, it is difficult to perform electrophoresis in the ionized layer 3.
Therefore, when the Cu / Te ratio is smaller than 1, the movement of Cu ions is suppressed and high-speed operation is difficult.

On the other hand, for example, when the composition ratio of Cu / Te is 1 or more, a Cu ₂ Te compound is formed, so it is considered that monovalent Cu ⁺ is generated.

In addition, when the Cu / Te ratio is particularly large and Cu is excessively contained, the Cu phase and the Cu ₂ Te phase are mixed in the equilibrium state, and these are difficult to mix so as to be separated even in the liquid phase. . Therefore, when there is too much Cu, the malfunction which a film | membrane peels arises.

Also, empirically, when only Cu and chalcogenide are used for the ionized layer, the adhesion with W, WN, TiN and other electrode layers formed of ordinary semiconductor materials is deteriorated, and film peeling is likely to occur.
Therefore, additional elements other than these are required to perform microfabrication to obtain the memory element 10.

However, when Ge is added to make the ionized layer CuTeGe, Cu ions may move without applying an electric field to the memory element, and a low resistance state after a write operation or a high resistance after an erase operation. It tends to be difficult to maintain the resistance value of the state.
When B (boron) is added to the ionized layer, the cause is not clear, but the resistance value in the high resistance state after the erase operation tends to be difficult to be maintained.

When Si is added to the ionization layer 3 as in the memory element 10 of the above-described embodiment, the low resistance state is presumably because the amorphous structure is more stable and the ion mobility is relatively small. Or it is easy to maintain the state where Cu is localized in a high resistance state.
In this case, the content of Si is preferably 10 atomic% to 45 atomic% in the entire ionized layer 3. When the amount of Si added is too small, the effect of the addition becomes small, and the retention characteristics become unstable. On the other hand, when the amount of Si added is too large, the movement of Cu ions becomes dull, and the operation speed of writing / erasing decreases.

  Thus, by adding Si to the ionized layer 3, Cu ions can be made difficult to move to some extent when an electric field is not applied to the memory element 10. Thereby, it is considered that an undesired change in resistance value can be suppressed and information retention characteristics can be improved.

  Specifically, the memory element 10 of the present embodiment can be manufactured as follows, for example.

First, a lower electrode 1 made of, for example, W is formed on a substrate on which a CMOS circuit such as a selection transistor is formed.
Thereafter, if necessary, oxides on the surface of the lower electrode 1 are removed by reverse sputtering or the like.

Next, the high resistance layer 2 made of a Gd oxide film is formed. For example, after forming a metal Gd film with a film thickness of, for example, 1 nm using a Gd target, the film is oxidized by oxygen plasma.
Next, an ionization layer 3, for example, a CuTeSi film is formed by DC magnetron sputtering.
Next, for example, a W film is formed as the upper electrode 4. In this way, a laminated film is formed.

  Thereafter, among the layers of the laminated film, the high resistance layer (oxide layer) 2, the ionized layer 3, and the upper electrode 4 are patterned by plasma etching or the like. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).

  Next, by forming a wiring layer connected to the upper electrode 4, the memory element 10 and a contact for obtaining a common potential are connected.

Next, a heat treatment process is performed on the laminated film.
In this way, the memory element 10 can be manufactured.

In the memory element 10 of the present embodiment, since the ionization layer 3 of the memory layer 5 contains Si, the recording / erasing operation characteristics are excellent and the information holding characteristics are excellent.
In particular, by setting the Cu / Te composition ratio in the ionized layer 3 to an appropriate range, preferably in the range of 1 to 3, the information retention characteristics can be further improved.

  In addition, when the memory element 10 of this embodiment is miniaturized, information can be easily held even when the current driving capability of the transistor is reduced. Therefore, by configuring the memory device using the memory element 10 of this embodiment, the memory device can be integrated (high density) or downsized.

Further, according to the memory element 10 of the present embodiment, each of the lower electrode 1, the oxide layer 2, the ionized layer 3, and the upper electrode 4 can be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

  Next, the memory element 10 and the memory cell array according to the above-described embodiment were actually manufactured, and the characteristics were examined.

Example 1
First, as shown in FIGS. 2 and 3, a MOS transistor Tr was formed on the semiconductor substrate 11.
Thereafter, an insulating layer was formed covering the surface.
Next, a via hole was formed in this insulating layer.
Subsequently, the via hole was filled with an electrode material made of WN (tungsten nitride) by CVD.
Next, the surface was planarized by CMP.
Then, by repeating these steps, the plug layer 15, the metal wiring layer 16, the plug layer 17, and the lower electrode 1 were formed, and the lower electrode 1 was further patterned for each memory cell.

Next, in order to remove the lower electrode 1 formed on the semiconductor substrate 11 on which the CMOS circuit including the MOS transistor Tr is formed, that is, the oxide on the upper surface of the tungsten nitride plug (WN plug), reverse using an RF power supply is performed. Etching was about 1 nm by sputtering.
At this time, it is desirable that the surface of the lower electrode 1 is ideally formed at the same height as the surrounding insulating layer and is flattened.

Next, a metal Cu film having a thickness of 1.0 nm is formed by DC magnetron sputtering, and the Gd film is oxidized for 10 seconds by RF plasma with O ₂ : Ar = 1: 3, chamber pressure 1 mTorr, and input power 500 W. Gd oxide was formed to form a high resistance layer (oxide layer) 2.

Next, a 30 nm thick CuTeSi film was deposited as the ionized layer 3.
The composition of the CuTeSi film was Cu 42% -Te 22% -Si 36% (atomic%). In this case, the Cu / Te ratio is 1.9.

Further, a W film having a film thickness of 20 nm was formed on the ionized layer 3 as the upper electrode 4.
In this way, the laminated films 1, 2, 3, and 4 constituting the memory element 10 shown in FIG. 1 were formed.

Thereafter, the high resistance layer 2, ionization layer 3, and upper electrode 4 formed on the entire surface are patterned so as to remain over the entire memory cell array portion (memory portion), thereby providing an external circuit for applying an intermediate potential (Vdd / 2). Etching was performed on the surface of the upper electrode 4 so that the contact portion to be connected was exposed.
Furthermore, an Al layer serving as a wiring was formed with a thickness of 200 nm so as to be connected to the exposed contact portion.

Subsequently, heat treatment was performed at 265 ° C. for 4 hours in a vacuum heat treatment furnace.
In this way, a memory cell array composed of the memory elements 10 shown in FIGS. 1 to 3 was produced and used as a sample of Example 1.

(Example 2)
The composition of the CuTeSi film of the ionized layer 3 is set to Cu 41% -Te 14% -Si 45% (atomic%). Otherwise, a memory cell array composed of memory elements is fabricated in the same manner as in Example 1, and the sample of Example 2 did. In this case, the Cu / Te ratio is 2.9.

(Example 3)
The composition of the CuTeSi film of the ionized layer 3 was set to Cu 44% -Te 30% -Si 26% (atomic%), and the other components were prepared as in Example 1 to produce a memory cell array composed of memory elements. did. In this case, the Cu / Te ratio is 1.5.

Example 4
The composition of the CuTeSi film of the ionized layer 3 was set to 46% Cu-Te 40% -14% Si (atomic%), and the others were made as in Example 1 to produce a memory cell array composed of memory elements. did. In this case, the Cu / Te ratio is 1.15.

(Example 5)
The composition of the CuTeSi film of the ionized layer 3 was set to Cu 33% -Te 31% -Si 36% (atomic%), and the other was produced a memory cell array composed of memory elements as in Example 1, and the sample of Example 4 did. In this case, the Cu / Te ratio is 1.1.

(Comparative Example 1)
The composition of the CuTeSi film of the ionized layer 3 was set to Cu 24% -Te 33% -Si 43% (atomic%). Other than that, a memory cell array composed of memory elements was fabricated in the same manner as in Example 1, and the sample of Comparative Example 1 did. In this case, the Cu / Te ratio is 0.7.

(Comparative Example 2)
The composition of the CuTeSi film of the ionized layer 3 was set to Cu 29% -Te 19% -Si 53% (atomic%). Otherwise, a memory cell array composed of memory elements was prepared in the same manner as in Example 1, and the sample of Comparative Example 2 did. In this case, the Cu / Te ratio is 1.5.

(Comparative Example 3)
The composition of the CuTeSi film of the ionized layer 3 was set to Cu 57% -Te 35% -Si 8% (atomic%). Other than that, a memory cell array composed of memory elements was fabricated in the same manner as in Example 1, and the sample of Comparative Example 3 did. In this case, the Cu / Te ratio is 1.6.

(Comparative Example 4)
The composition of the CuTeSi film of the ionization layer 3 is set to Cu 55% -Te 13% -Si 32% (atomic%), and the others are manufactured as in the first embodiment. did. In this case, the Cu / Te ratio is 4.2.

  Table 1 shows the composition of the CuTeSi film and the Cu / Te ratio for these examples and comparative examples.

(Repeated operation characteristics)
First, a memory that selects the upper wiring connected to the upper electrode 4 as an intermediate potential of Vdd / 2 for a total of 20 memory elements 10 in 10 × 2 columns in the memory cell array of the sample of the first embodiment. A voltage of 1.8 V is applied to the gate electrode of the cell, that is, the word line WL to turn it on, and the electrode connected to the source / drain 13 of the transistor Tr that is not connected to the memory element 10, that is, A “write operation” was performed by applying a write voltage Vw of 2.5 V with a pulse width of 10 μs (microseconds) to the bit line BL. Then, after this writing operation, the resistance value of each memory element 10 was read.
Subsequently, a voltage of 3.0 V is applied to the gate electrode, that is, the word line WL to turn it on, and the same 20 memory elements 10 in the memory cell array are subjected to −2. An “erasing operation” was performed by applying an erasing voltage Ve of 5 to 0.7 V. Then, after this erasing operation, the resistance value of each memory element 10 was read.
This write operation and erase operation were repeated 1000 times for the memory cell array, and the repeated operation characteristics were evaluated.
FIG. 4 shows the repeated operation characteristics of the sample of Example 1 obtained in this way. In FIG. 4, the horizontal axis indicates the number of repetitions, and the resistance value after the write operation and the resistance value after the erase operation are respectively shown.

  From FIG. 4, it can be seen that both the resistance value after the write operation and the resistance value after the erase operation are small in the change due to the repeated operation, and the low resistance state and the high resistance state are maintained. It can also be seen that a sufficient difference in resistance value is obtained.

  Note that the high-speed operation characteristics can be evaluated by narrowing the pulse width during the write operation and the erase operation.

(Information retention characteristics)
For the sample memory cell array of the first embodiment, one column is stopped by the write operation and the remaining one column is erased, out of a total of 20 memory elements 10 of 10 columns × 2 columns in the memory cell array. The program operation and the erase operation were repeated 1000 times under the same conditions (voltage / pulse width) as the measurement of the repeated operation characteristics described above, so as to stop at the operation. And the resistance value in the state which each memory element 10 stopped was measured.
Subsequently, the sample was held in an oven at 120 ° C. for 1 hour, and a high temperature accelerated holding test was performed.
Thereafter, the resistance value of each identical memory element 10 was measured.
The same measurement is performed by changing the erase voltage in increments of 0.2 V in the range of −0.7 V to −2.5 V, and comparing the resistance value before and after the high temperature accelerated holding test to thereby improve the information holding characteristics. evaluated.

  As a measurement result, the relationship between the erase voltage Ve and the resistance value before and after the high temperature accelerated holding test is shown in FIG. The solid line is the resistance value before the high temperature accelerated holding test, and the dotted line is the resistance value after the high temperature accelerated holding test.

  From FIG. 5, when the erase voltage Ve is small, the resistance value in the high resistance state is slightly lower due to the high temperature acceleration, but the resistance value is sufficiently higher than the resistance value in the low resistance state, and the information is retained without any problem. You can see that it is made.

For each of the samples of Examples 2 to 5 and Comparative Examples 1 to 4, similar to the sample of Example 1, repeated operation and a high temperature accelerated holding test were performed to examine information holding characteristics.
In the following, the measurement results of the obtained samples are extracted and discussed.

First, the range of the Cu / Te ratio of CuTeSi of the ionized layer 3 will be described.
The lower limit of the Cu / Te ratio will be described.
FIG. 6 and FIG. 7 show the relationship between the erasing voltage Ve and the resistance value before and after the high temperature acceleration test, respectively, as measurement results obtained by examining the high temperature acceleration holding characteristics of the samples of Example 5 and Comparative Example 1. 6 shows the measurement result of the sample of Example 5, and FIG. 7 shows the measurement result of the sample of Comparative Example 1.

As shown in FIG. 6, in Example 5 in which the Cu / Te ratio is 1.1 and is within the scope of the present invention, a clear difference in resistance value is observed after the write operation and after the erase operation. The resistance change after high temperature acceleration is small.
On the other hand, as shown in FIG. 7, in Comparative Example 1 in which the Cu / Te ratio is 0.7, there is no clear difference in resistance value between the write operation and the erase operation, and the resistance value after the write operation. Is not low. That is, the writing operation is not performed correctly.
As will be described later, when the Cu / Te ratio is larger than 1.1 in Example 5, the write operation and the erase operation are correctly performed.
Therefore, when the Cu / Te ratio is less than 1, as in the case of the Cu / Te ratio of Comparative Example 1, the write operation and the erase operation cannot be performed correctly.

Next, the upper limit of the Cu / Te ratio will be described.
Each sample of Example 1, Example 2, and Comparative Example 4 was examined for the presence or absence of film peeling after fabrication of the memory cell array. The examination results are shown in Table 2.

  From Table 2, film peeling does not occur in Example 1 and Example 2, but film peeling occurs in Comparative Example 4.

  Next, FIG. 8 and FIG. 9 show the relationship between the erase voltage Ve and the resistance value before and after the high temperature acceleration test, respectively, as measurement results of examining the high temperature acceleration holding characteristics of the samples of Example 2 and Comparative Example 4. FIG. 8 shows the measurement results of the sample of Example 2, and FIG. 9 shows the measurement results of the sample of Comparative Example 4.

As shown in FIG. 8, the Cu / Te ratio is 2.9, and in Example 2, which is within the scope of the present invention, a clear difference in resistance value is observed after the write operation and after the erase operation. The resistance change after high temperature acceleration is small.
On the other hand, as shown in FIG. 9, in Comparative Example 4 in which the Cu / Te ratio is 4.2, it was impossible to perform the writing operation and the erasing operation because the film was peeled off.
As described above, in Example 2 in which the Cu / Te ratio is 2.9, write operation / erase operation and information retention are possible, but in Comparative Example 4 in which the Cu / Te ratio is 4.2, film peeling occurs. The operation becomes impossible.
Therefore, it is probable that when the Cu / Te ratio exceeds 3, the memory operation characteristics are significantly deteriorated due to the film peeling.

Although the cause of this film peeling is not necessarily clear, when considering a Cu-Te binary alloy, the Cu phase and the Cu ₂ Te phase exist in an equilibrium state in a composition in which the Cu amount exceeds 67%. Even in the liquid phase, phase separation occurs without mixing. For this reason, it is considered that the presence of excessive Cu probably causes the film to peel off because the amorphous structure is not stable even in the ionized layer and phase separation occurs.
Examples 1 and 2 in which the Cu / Te ratio is smaller than 3 show good memory operation and information retention characteristics as shown in FIGS.

  Therefore, from the above results, the Cu / Te ratio is desirably 1 or more and 3 or less.

Next, the range of the Si composition of CuTeSi of the ionized layer 3 will be described.
First, the lower limit of the Si amount will be described while comparing the evaluation results of Example 4 and Comparative Example 3 which are examples of the present invention.
FIG. 10 and FIG. 11 show the relationship between the erase voltage Ve and the resistance value before and after the high temperature acceleration test, respectively, as measurement results of examining the high temperature acceleration holding characteristics of the samples of Example 4 and Comparative Example 3. FIG. 10 shows the measurement result of the sample of Example 4, and FIG. 11 shows the measurement result of the sample of Comparative Example 3.

  In Comparative Example 3, it was impossible to perform the writing operation and the erasing operation because the film was peeled off.

As shown in FIG. 10, in Example 4, which is within the scope of the present invention, the difference between the resistance value after the write operation and the resistance value after the erase operation is about 1.9 V under the measurement conditions. Begins to decrease.
On the other hand, as shown in FIG. 11, in Comparative Example 3, when the erase voltage Ve is 1.3 V or more, the resistance value after the erase operation decreases, and the resistance value can be discriminated after the write operation and after the erase operation. Disappear.

Furthermore, an example of the repetition characteristics in the sample of Comparative Example 3 is shown in FIG.
As shown in FIG. 12, until the middle of the repetition, although there is a sufficient difference between the resistance values after the writing operation / after the erasing operation, the resistance value after the erasing operation starts when the number of repetition exceeds 100 times. Is decreasing rapidly. This rapid decrease in the resistance value occurs frequently when the Si amount is less than 10%. On the other hand, as in Example 4 of the present invention, when the Si amount exceeds 10% and is contained by 14%, this decrease in resistance value is greatly relieved.
The cause of this sudden decrease in resistance value is not necessarily clear, but if the amount of Si is too small, Cu ions move very easily and the ion mobility becomes excessively large. Therefore, excessive reduced metal state Cu is deposited on the lower electrode side, or the oxide film on the lower electrode is dielectrically broken, and this can be pulled back into the ionization layer again in a normal erase operation. It is thought that it will disappear.
Accordingly, the Si amount is desirably at least 10% or more.

Next, the upper limit of the Si content of CuTeSi in the ionized layer 3 will be described while comparing the results of Example 2 and Comparative Example 2.
FIG. 13 and FIG. 14 show the relationship between the erase voltage Ve and the resistance value before and after the high temperature acceleration test, respectively, as measurement results of examining the high temperature accelerated holding characteristics of the samples of Example 2 and Comparative Example 2. FIG. 13 shows the measurement results of the sample of Example 2, and FIG. 14 shows the measurement results of the sample of Comparative Example 2.

As shown in FIG. 13, in Example 2, which is within the scope of the present invention, the Si amount is 45% and a relatively large amount of Si is contained. In comparison, it starts to decrease slightly due to the high temperature accelerated holding test. However, in the second embodiment, there is a possibility that good memory characteristics can be obtained if conditions are set appropriately.
However, as shown in FIG. 14, in Comparative Example 2, the Si amount is 53% and more Si is contained, so that the retention performance of the high resistance value after the erasing operation is further lowered as compared with Example 2. is doing.
Although the cause is not necessarily clear, when Cu is excessively contained in the CuTeSi of the ionized layer 3 as described above, the high resistance holding performance is deteriorated.
Therefore, if the amount of Si contained in the CuTeSi ionized layer is too large, desirable information retention performance cannot be obtained, so the Si amount is desirably 45% or less.

  From the above, it is desirable that the amount of Si in the ionized layer using CuTeSi is 10% or more and 45% or less.

  Such a preferable Cu-Te-Si composition range showing the good memory operation characteristics and information retention characteristics of the present invention is expressed in the ternary map shown in FIG. It becomes.

A memory device (memory device) can be configured by arranging a large number of memory elements, for example, in a column or matrix, using the memory elements of the present invention as shown in the above-described embodiments and the like. .
At this time, a memory cell is configured by connecting a MOS transistor or a diode for selecting the element to each memory element as necessary.
Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. It is possible to apply any memory form such as (memory).

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element of the present invention. It is a schematic block diagram (sectional drawing) of the memory cell array using the memory element of FIG. FIG. 2 is a schematic configuration diagram (plan view) of a memory cell array using the memory element of FIG. 1. It is a figure which shows the repetitive operation characteristic of the sample of Example 1. It is a figure which shows the relationship between the erasing voltage of the sample of Example 1, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage of the sample of Example 5, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erase voltage of the sample of the comparative example 1, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage of the sample of Example 2, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage of the sample of the comparative example 4, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage of the sample of Example 4, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage of the sample of the comparative example 3, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the repetition operation characteristic of the sample of the comparative example 3. FIG. It is a figure which shows the relationship between the erasing voltage Ve of the sample of Example 2, and the resistance value before and behind a high temperature accelerated holding test. It is a figure which shows the relationship between the erasing voltage Ve of the sample of the comparative example 2, and the resistance value before and behind a high temperature accelerated holding test. It is a ternary map expressing a suitable Cu-Te-Si composition range.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 High resistance layer, 3 Ionization layer, 4 Upper electrode, 5 Memory layer, 10 Memory element, Tr MOS transistor, BL bit line, WL Word line, PL plate electrode

Claims (3)

A memory layer is sandwiched between the first electrode and the second electrode,
The memory layer is composed of an ionized layer containing Cu to be ionized and a high resistance layer having a sufficiently higher resistance value than the ionized layer,
The ionized layer is a CuTeSi film;
In the ionized layer, the composition ratio of Cu content (atomic%) / Te content (atomic%) is 1 or more and 3 or less,
The Si content (atomic%) in the ionized layer is 10% or more and 45% or less ,
The memory element , wherein the high resistance layer is made of an oxide containing one or more elements selected from rare earth elements, Si, and Cu . A memory layer is sandwiched between the first electrode and the second electrode, and the memory layer includes an ionized layer containing Cu to be ionized and a high resistance having a sufficiently higher resistance value than the ionized layer. The ionized layer is a CuTeSi film, and the composition ratio of Cu content (atomic%) / Te content (atomic%) is 1 or more and 3 or less in the ionized layer, A memory element having a Si content (atomic%) of 10% or more and 45% or less , wherein the high resistance layer is made of an oxide containing one or more elements selected from rare earth elements, Si, and Cu ;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device in which a large number of the storage elements are arranged . The storage device according to claim 2 , wherein in a plurality of adjacent storage elements, at least a part of layers constituting the storage element is formed in common by the same layer.

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