JP2008153375A - Storage element and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage element having a structure that film in the element structure is not peeled off and the storage element can be manufactured easily and at a high density. <P>SOLUTION: Respective memory cells are configured by a resistance change element which is configured to have a storage layer between two electrodes, and in which a resistance value of the storage layer changes reversibly by applying a potential of a different pole to the two electrodes. In a plurality of adjacent memory cells, at least a partial layer containing the storage layer of the resistance change element is formed commonly with the identical layer, and an ion source layer containing: a metal element of one kind or more selected from Cu, Ag and Zn; a chalcogen element of one kind or more selected from Te, S and Se; and Si or Ge is laminated on the storage layer. The storage element is configured to have an atomic composition ratio of the metal element to the chalcogen element which is 0.5 to 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

In addition, there is a memory element that can easily and stably record and read information by stabilizing the electrical characteristics such as the resistance value of the memory element due to heat addition of the memory device and the recording / erasing operation voltage. It has been proposed (see, for example, Patent Document 2).
This memory element is a memory element configured by sandwiching a memory layer between two electrodes. The memory layer contains a rare earth element, and a Cu layer is formed in the memory layer or in contact with the memory layer. , Ag, and Zn, and any element selected from Te, S, and Se is contained in the memory layer or in a layer in contact with the memory layer.

This memory element can employ a structure in which each memory cell is isolated and electrically separated from surrounding memory cells, as in various general memories.
For example, a lower electrode for applying an operating voltage, an ion source layer containing any element of Cu, Ag, and Zn, a high-resistance memory layer containing a rare earth element, and an upper electrode are separated for each memory cell. To do.

By the way, as the storage capacity of the memory increases, it is necessary to reduce the size of the memory cell.
In view of the above, it has been proposed to simplify the manufacturing process by partially sharing the memory layers and electrodes of a plurality of adjacent memory cells in the memory element described above (see, for example, Patent Document 3). .
For example, in a structure in which a high-resistance storage layer and an ion source layer containing any one element of Cu, Ag, and Zn are stacked in this order on a lower electrode to which an operating voltage is applied, memory cells adjacent to each other by the high-resistance storage layer It can be electrically separated. Therefore, the lower electrode can be separated by each memory cell, and the memory layer, the ion source layer, and the upper electrode can be formed on the lower electrode in common by adjacent memory cells.
By adopting such a configuration, it is possible to relax restrictions on miniaturization of the size of the memory cell and to improve the density of the memory cell.

Special Table 2002-536840 Publication JP 2005-197634 A JP 2006-40946 A

The lower electrode occupies only a small area in the plane of which the insulating layer occupies most.
When each memory cell is isolated, each layer such as a memory layer formed on the lower electrode is separated by each memory cell similarly to the lower electrode, so that the proportion of the portion connected to the lower electrode is large. The adhesion strength with the lower electrode is not a problem.
However, in the case of the memory structure in which the memory layer, the ion source layer, and the upper electrode are formed in common with the adjacent memory cell, the layer formed in common is disposed on the plane that occupies most of the insulating layer. Is done. For this reason, when the adhesion strength as a whole becomes weak, film peeling occurs.

  In particular, the ion source layer contains a large amount of an element having a low adhesion strength when laminated on an oxide such as Cu, and the memory layer disposed below the oxide layer is also an oxide having a high resistance. If used, film peeling is likely to occur. If it is local, it may cause unstable operation as a memory and lead to destruction of the element.

  In order to solve the above-described problems, the present invention provides a memory element and a memory device having a structure in which the element structure does not peel off and can be manufactured easily and at a high density.

  The memory element of the present invention is configured to have a memory layer between two electrodes, and a resistance change in which the resistance value of the memory layer changes reversibly by applying potentials having different polarities to the two electrodes. Each memory cell is constituted by an element, and in a plurality of adjacent memory cells, at least a part of the layer including the memory layer of the resistance change element is formed in common by the same layer, and Cu, Ag is formed on the memory layer. 1 or more metal elements selected from Zn, one or more chalcogen elements selected from Te, S and Se, and an ion source layer containing Si or Ge, and a metal element for the chalcogen elements The atomic composition ratio is 5 to 0.5.

  Further, the memory device of the present invention has a memory layer between two electrodes, and the resistance value of the recording layer reversibly changes by applying potentials having different polarities to the two electrodes. Each memory cell is constituted by a resistance change element, and in a plurality of adjacent memory cells, at least a part of the layer including the resistance change element storage layer is formed in common by the same layer, and Cu, A metal with respect to a chalcogen element formed by laminating an ion source layer containing one or more metal elements selected from Ag, Zn, one or more chalcogen elements selected from Te, S, Se, and Si or Ge. A memory element having an atomic composition ratio of 5 to 0.5; a wiring connected to the first electrode side; and a wiring connected to the second electrode side; Many elements are arranged And wherein the door.

  According to the configuration of the memory element and the memory device of the present invention described above, the recording layer is provided between the two electrodes, and the recording layer is reversibly applied by applying potentials having different polarities to the two electrodes. Since each memory cell is configured by a resistance change element that changes the resistance value of the resistance, the resistance value of the resistance change element can be reversibly changed between a high resistance and a low resistance. The resistance state of the element can be stored in the memory cell as information.

  In addition, in a plurality of adjacent memory cells, at least a part of the layers constituting the recording layer of the resistance change element is formed in common by the same layer, so that it is formed in common when manufacturing the memory element. For the existing layers, local recording film deposition or patterning for each memory cell is not required, so that the patterning accuracy is reduced and patterning can be easily performed.

  Further, in the ion source layer formed on the memory layer, the atomic composition ratio of the metal element to the chalcogen element is 5 to 0.5, so that the device structure is manufactured with a stable yield without causing film peeling. can do.

According to the above-described present invention, when the memory element is manufactured, the layer formed in common has a reduced patterning accuracy and can be easily patterned. Since generation | occurrence | production can be suppressed, a manufacturing yield can be improved significantly.
Therefore, even when the size of the memory cell is reduced, the memory element can be easily manufactured with a high yield, so that the density of the memory cell can be increased. As a result, the storage capacity of the storage element can be increased and the memory can be downsized.
Therefore, according to the present invention, a highly reliable storage device can be configured.
In addition, the storage device can be highly integrated (densified) and downsized.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element is shown in FIG. FIG. 2 shows a schematic plan view of the memory element of this embodiment.
This memory element is configured by arranging a large number of variable resistance elements 10 constituting a memory cell in an array.

  As shown in FIG. 1, in this memory cell array, the resistance change element 10 constituting each memory cell shares the memory layer 2, the ion source layer 3, and the upper electrode 4 over the entire memory cell. In other words, each resistance change element 10 is composed of the same memory layer 2, ion source layer 3, and upper electrode 4.

  For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.

  The memory layer 2 can use metal elements, rare earth elements, oxides of these mixtures, nitrides, or semiconductors, and can be configured by adding Cu, noble metals, or the like to them.

  For the upper electrode 4, a normal semiconductor wiring material can be used in the same manner as the lower electrode 1.

The ion source layer 3 contains at least one metal element of Cu, Ag, and Zn. Further, the ion source layer 3 contains at least one of Te, Se, and S chalcogen elements, and Si or Ge.
As this ion source layer 3, for example, CuTeSi, GeSbTeSi, CuGeTeSi, AgGeTeSi, AgTeSi, ZnTeSi, ZnGeTeSi, CuSSi, CuGeSSi, CuSeSi, CuGeSeSi or the like can be used.
Further, the ion source layer 3 may further contain boron or a rare earth element.

In particular, in order to limit the portion where the resistance value changes to the memory layer 2 having a relatively high resistance value, the ion source layer 3 is made of a material having a sufficiently low resistance compared to the high resistance memory layer 2 ( For example, it is preferable to use a material that is lower than the resistance value when the memory layer 2 is on.
Therefore, it is desirable to use Te as the chalcogenide element of the ion source layer 3. And it is desirable to contain the metal element of Cu, Ag, Zn which can move easily as a cation. Therefore, the ion source layer 3 is desirably formed of a material mainly composed of CuTe, AgTe, or ZnTe, for example.
Furthermore, it is preferable to use Cu as an element that becomes a cation of the ion source layer 3 and to contain CuTe. Thereby, the resistance of the ion source layer 3 can be lowered, the resistance change of the ion source layer 3 can be made sufficiently smaller than the resistance change of the memory layer 2, and the stability of the memory operation can be improved. .

As described above, the ion source layer 3 of the present embodiment contains any metal element selected from Cu, Ag, and Zn and any chalcogen element selected from Te, S, and Se.
In the ion source layer 3, the atomic composition ratio of the metal element to the chalcogen element, for example, the atomic composition ratio of Cu: Te (Cu / Te ratio) is 0.5: 1 (0.5) to 5: 1 (5 ) Is preferable.
The atomic composition ratio of the metal element to the chalcogen element in the ion source layer 3 is hereinafter referred to as a Cu / Te ratio, representative of Cu, Ag, Zn, and Te, S, Se. However, the selection of these elements is not limited to Cu and Te as described above.

  By setting the Cu / Te ratio to 5 or less, the ion source layer 3 containing Cu, Ag, and Zn can be manufactured with a stable yield without causing film peeling.

In addition, since elements are driven using transistors, there are limitations on voltage, current, and the like.
If the amount of Cu, Ag, and Zn in the ion source layer is too small, the number of ions itself decreases. For this reason, although the operation is performed, the speed is decreased and the threshold values of the voltage and current required for driving are increased, so that the recording / erasing operation cannot be performed as a memory.
Therefore, the Cu / Te ratio needs to be 0.5 or more as an operable range as a memory.

  More preferably, by setting the above-described Cu / Te ratio to 1 to 2, it is possible to realize a memory having excellent data retention characteristics after recording and erasing as well as being operable as a memory.

Further, the ion source layer 3 of the present embodiment contains Si or Ge.
When an appropriate amount of Si and Ge is contained in the ion source layer 3, the amorphous structure of the ion source layer 3 can be further stabilized, and state changes such as crystallization due to heat received during the process are suppressed. Therefore, it can be expected to be thermally stable, and the stability of the memory operation related to heat is improved.

Furthermore, by adding Si and Ge to the ion source layer 3, the ion mobility becomes relatively small, so that it is easy to maintain a state where Cu is localized in a low resistance state or a high resistance state.
In addition, when Si or Ge is added to the ion source layer 3, a change in characteristics with respect to temperature can be suppressed as compared with a case where Si or Ge is not added.

  However, if Si and Ge are added excessively, adverse effects such as hindering the movement of ions will be adversely affected. This phenomenon is considered to have a similar effect not only on Si but also on Ge, and the composition ratio of Si or Ge element or the total composition ratio of Si and Ge is applied to the entire ion source layer 3. On the other hand, when it exceeded 0.45, it was experimentally confirmed to have an adverse effect.

In the memory elements shown in FIGS. 1 and 2, the upper electrode 4 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. The resistance change element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
Although not shown in the drawings, the structure such as the lower electrode 1 is filled with an insulating layer such as SiO ₂ or Si ₃ N ₄ . On this plane, the memory layer 2, which is a high resistance film, the ion source layer 3, and the upper electrode 4 are laminated in this order.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 1, each resistance change element 10 constituting each memory cell of the memory cell array is formed above a MOS transistor Tr formed on a semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the resistance change element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. The metal wiring layer 16 is connected to a bit line BL (see FIG. 2) which is the other address wiring of the memory element.

  In FIG. 2, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 2, reference numeral 21 denotes a contact portion that communicates with the lower electrode 1 of the resistance change element 10, and 22 denotes a contact portion that communicates with the bit line BL.

  The memory layer 2 having the above-described configuration has a characteristic that impedance changes when a voltage pulse or a current pulse is applied.

The resistance change element 10 of the present embodiment can be operated as follows to store information.
First, for example, a positive potential (+ potential) is applied to the upper electrode 4, and a positive voltage is applied to the resistance change element 10 so that the lower electrode 1 side becomes negative. As a result, Cu, Ag, and Zn ions are ion-conducted from the ion source layer 3 in the memory layer 2 and are combined with electrons on the lower electrode 1 side to be deposited or remain diffused in the memory layer 2. .
Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the memory layer 2, or a large number of defects due to Cu, Ag, Zn are formed inside the memory layer 2. Resistance value becomes low. Each layer other than the memory layer 2 originally has a lower resistance value than the resistance value of the memory layer 2 before recording. Therefore, by lowering the resistance value of the memory layer 2, the resistance value of the entire resistance change element 10 is also lowered. can do.

  Thereafter, when the positive voltage is removed and the voltage applied to the resistance change element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc. In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 4, A negative voltage is applied to the resistance change element 10 so that the lower electrode 1 side is positive. As a result, the current path formed in the memory layer 2 or the Cu, Ag, Zn forming the impurity level is ionized, and the ion conduction in the memory layer 2 is dissolved in the ion source layer 3 or Te, It combines with Se and S to form a compound such as Cu ₂ Te.

  As a result, the current path or impurity level due to Cu, Ag, or Zn disappears or decreases from within the memory layer 2, and the resistance value of the memory layer 2 increases. Since each layer other than the memory layer 2 originally has a relatively low resistance value, the resistance value of the entire resistance change element 10 can be increased by increasing the resistance value of the memory layer 2.

  Thereafter, when the negative voltage is removed and the voltage applied to the resistance change element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  In particular, the ion source layer 3 contains an element selected from Te, S, and Se, that is, a chalcogen element, in addition to the above metal elements (Cu, Ag, Zn), so that the metal in the ion source layer 3 The element and the chalcogen element are combined to form a metal chalcogenide layer.

  This metal chalcogenide layer mainly has an amorphous structure. For example, when a positive potential is applied to the upper electrode 4 side that is in contact with the ion source layer 3 made of a metal chalcogenide layer, the metal element (Cu, Ag, Zn) contained in the metal chalcogenide layer is ionized to exhibit a high resistance. 2 and diffuses into a portion of the lower electrode 3 and combines with electrons to be deposited. Alternatively, the resistance of the memory layer 4 is reduced by remaining in the memory layer 2 and forming an impurity level of the insulating film. This makes it possible to record information.

  From this state, when a negative potential is applied to the upper electrode 4 side in contact with the ion source layer 2 made of a metal chalcogenide layer, the metal elements (Cu, Ag, Zn) deposited on the lower electrode 1 side are ionized again, Return to the metal chalcogenide layer. Thereby, the resistance of the memory layer 2 returns to the original high state, and the resistance of the resistance change element 10 is also increased, so that the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the variable resistance element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  The material of the memory layer 2 is preferably a material that exhibits a high resistance value in the initial state before recording and in the state after erasing.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the resistance change element 10 and the material composition of the memory layer 2. The resistance value of the memory layer 2 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials. When the initial resistance value is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio of the initial resistance value to the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance after recording is It is sufficient if the value is 50Ω, or the resistance value before recording is 100 kΩ, and the resistance value after recording is 50 kΩ, and the initial resistance value of the memory layer 2 is set to satisfy such a condition. .
The resistance value of the memory layer 2 can be controlled by, for example, the amount of oxygen contained in the Cu oxide of the memory layer 2 before the heat treatment, the amount of rare earth elements contained in the ion source layer 3, and the heat treatment temperature. It is.

  According to the configuration of the resistance change element 10 described above, the memory layer 2 and the ion source layer 3 containing Cu, Ag, and Zn are sandwiched between the lower electrode 1 and the upper electrode 4. For example, when a positive voltage (+ potential) is applied to the upper electrode 4 so that the lower electrode 1 side becomes negative, a current path containing a large amount of Cu, Ag, and Zn is formed in the memory layer 2. In addition, by forming a large number of defects due to Cu, Ag, and Zn in the memory layer 2, the resistance value of the memory layer 2 is lowered, and the resistance value of the entire resistance change element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the resistance change element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored by using a change in resistance value of the resistance change element 10, particularly a change in resistance value of the memory layer 2, even when the resistance change element 10 is miniaturized, information is stored. Recording and storing of recorded information becomes easy.

Further, for example, when used in a storage device that can be erased in addition to recording such as RAM and EEPROM, a negative voltage (−potential) is applied to the upper electrode 4 with respect to the resistance change element 10 in the state after recording described above. ) To make the lower electrode 1 side positive.
As a result, current paths or defects due to Cu, Ag, and Zn formed in the memory layer 2 disappear, the resistance value of the memory layer 2 increases, and the resistance value of the entire resistance change element 10 increases. . Then, by stopping the application of the negative voltage so that no voltage is applied to the resistance change element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased. .

  Furthermore, according to the structure of the resistance change element 10 described above, the ion source layer 3 contains a chalcogenide element of Te, S, or Se in addition to the metal element of Cu, Ag, or Zn. Ionization is promoted.

By arranging a large number of variable resistance elements 10 having the above-described configuration in a matrix, a storage device (memory device) can be configured.
For each resistance change element 10, a wiring connected to the lower electrode 1 side and a wiring connected to the upper electrode 4 side are provided. For example, each resistance change element 10 is arranged near the intersection of these wirings. What should I do?

The memory cell array shown in FIGS. 1 and 2 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.

Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 4 (plate electrode PL), the resistance value of the resistance change element 10 goes to a low resistance state. Transition. Thereby, information can be recorded in the resistance change element 10 of the selected memory cell.
Further, when a voltage having a positive potential is applied to the lower electrode 1 as compared with the potential of the upper electrode 4 (plate electrode PL), the resistance value of the resistance change element 10 transitions to the high resistance state again. Thereby, the recorded information can be erased from the variable resistance element 10 of the selected memory cell.

In order to read the recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the resistance change element 10 is determined. Thus, a different current or voltage is detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the resistance change element 10 changes.

By the way, in the ionization behavior excited by applying a voltage to the resistance change element 10 described above, or the change in the resistance value due to the operation of the ions, the threshold voltage and the writing and erasing speed when the resistance value changes are stored. It depends greatly on the state of layer 2.
Generally, the shorter the time during which the write voltage is applied, the higher the write voltage is required. Similarly, in the erase operation, the shorter the time during which the erase voltage is applied, the greater the voltage required for erasure.
For this reason, in order to form the variable resistance element 10 that can operate at a higher speed, the storage threshold voltage is kept low, and in order to perform a balanced operation for both recording and erasing, a storage layer is used with an appropriate method and conditions. 2 must be formed.

For example, when the rare earth element oxide is formed as the memory layer 2 and the ion source layer 3 containing the rare earth element is formed thereon, the heat applied in the manufacturing process for forming the semiconductor and the subsequent heat treatment, When the rare earth element in the ion source layer 3 diffuses into the memory layer 2, the thickness of the memory layer 2 may increase.
As a result of the increase in the thickness of the storage layer 2 as described above, the operation threshold voltage increases, and the writing / erasing speed decreases.
Therefore, it can be seen that it is desirable to form the memory layer 2 made of a rare earth oxide by an appropriate method and conditions.

According to the memory element of the present embodiment, the memory layer 2, the ion source layer 3, and the variable resistance element layers of the upper electrode 4 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

In the resistance change element 10 of the above-described embodiment, the ion source layer 3 can be formed by a method of forming a film using a target manufactured with the determined composition. In addition, using a device that can form multiple materials at the same time, a method for depositing various elements at the same time and forming a film formation time so that each material does not form a layer is set. It is also possible to make adjustments by using a method of repeatedly forming layers.
In the above-described method of repeatedly forming layers, the composition of the ion source layer 3 can be changed by adjusting the film formation rate of each material.

  In the resistance change element 10 of the above-described embodiment, the ion source layer 3 and the upper electrode 4 are separately formed of different materials, but elements (Cu, Ag, Zn) that serve as ion sources in the electrodes. The electrode layer and the ion source layer can also be used as a structure.

Next, a memory element was actually manufactured and its characteristics were examined.
A circular lower electrode 1 made of W and having a diameter of 0.3 μmφ was formed on a substrate on which a CMOS circuit such as a selection transistor was formed.
Next, a gadolinium (Gd) oxide layer 3 nm was formed as the memory layer 2 on the substrate where the lower electrode 1 was exposed on the surface.
Next, the ion source layer 3 is formed with a CuTeSiGe film having a thickness of 20 nm by DC magnetron sputtering.
Next, a W film having a thickness of 200 nm is formed as the upper electrode 4.
Thereafter, an area including a plurality of elements of the memory layer 2, the ion source layer 3, and the upper electrode 4 deposited on the wafer was patterned by a photolithography technique using a plasma etching apparatus.
In this way, the variable resistance element 10 having the structure shown in FIG. 1 was fabricated and used as a sample.

(Experiment 1)
First, in the variable resistance element described above, the atomic composition ratio (Cu / Te ratio) of the Cu element to the Te element of the CuTeSiGe film of the ion source layer 3 was changed, and samples of the variable resistance elements 10 were produced.
Specifically, in the CuTeSiGe ion source layer, the composition of Si and Ge is constant at Si 25% -Ge 10% (atomic%), and the Cu / Te composition ratio is 1.5, 1.87, 2.5, The ion source layer 3 was produced by changing the composition of Cu and Te so as to be 2.8, 3.75, 5, 5.6, and 7.5. Next, heat treatment was performed on the manufactured memory element at 200 ° C. for 1 hour.
Table 1 shows the results of examining the state of film peeling of the ion source layer 3 in the memory element after the heat treatment.

  From Table 1, it can be seen that if the atomic composition ratio of Cu element to Cu element (Cu / Te ratio) is 5 or less, film peeling does not occur. In contrast, when the Cu / Te ratio is greater than 5, it is observed that film peeling occurs.

In general, it is considered that Cu and Te are bonded in the ion source layer 3. However, when a Cu-Te binary alloy is considered, a Cu phase of a Cu / Te ratio exceeding 5 has a Cu phase. And Cu ₂ Te phase exist in an equilibrium state, and each phase separates without being mixed even in the liquid phase. From this, if Cu enters excessively, Cu—Te and Cu exist separately, and the amorphous structure is not stable in the ion source layer 3, and phase non-uniformity occurs. It is considered that peeling occurs.
This shows that the upper limit of the Cu / Te ratio of the ion source layer 3 needs to be 5 or less.

(Experiment 2)
Next, in the same memory element as in Experiment 1, the ion source layer 3 was fabricated such that the Cu / Te ratio was 0.4 and 0.5.
FIG. 3 shows the cumulative occurrence probability of the resistance value obtained by repeatedly performing the recording / erasing operation 1000 times on the manufactured memory element.
The conditions at this time were a recording / erasing pulse width of 10 μsec, a recording / erasing voltage of 2.5 V, and the maximum conditions of the transistors used in this experiment.

FIG. 3A shows the cumulative occurrence probability of the storage element when the Cu / Te ratio is 0.4, and FIG. 3B shows the cumulative occurrence probability of the storage element when the Cu / Te ratio is 0.5. It is.
3A and 3B, the vertical axis represents the cumulative sound frequency distribution (%), and the horizontal axis represents the element resistance (Ω). The broken line indicates the distribution of the recording resistance, and the solid line indicates the distribution of the erasing resistance.

In the memory element shown in FIG. 3B in which the Cu / Te ratio of the ion source layer 3 is 0.5, although the separation between the recording resistance and the erasing resistance is incomplete on the high resistance side, there is no difference in height. It can be seen that the recording / erasing operation is being performed.
On the other hand, in the memory element shown in FIG. 3A in which the Cu / Te ratio of the ion source layer 3 is 0.4, the recording resistance and the erasing resistance distribution overlap, and the recording / erasing operation is performed. You can see that it is not.

When the Cu / Te ratio of the ion source layer 3 is 0.4, the reason why the recording / erasing operation of the storage element is not performed is that the ratio of Cu ions, which are the players of the operation, is higher than Te that promotes ionization. This seems to be because there is too little.
Even when the Cu / Te ratio is 0.4, the recording / erasing operation can be performed by greatly increasing the recording / erasing pulse width or by supplying the necessary voltage / current from the outside without using a transistor. Although there is such a method, it is not practical.

  As described above, according to Experiment 1 and Experiment 2, in the memory element of this configuration, the ion source layer 3 can be manufactured with high yield without causing film peeling, and in order to operate as the memory element, Cu in the ion source layer 3 It can be seen that the / Te ratio needs to be 0.5 or more and 5 or less.

(Experiment 3)
Next, in the same memory element as in Experimental Example 1, the configuration of the ion source layer 3 has a Cu / Te ratio of 2 (Cu: Te = 66: 34), 1.5 (Cu: Te = 60: 40), 1.27 (Cu: Te = 56: 44) and 1 (Cu: Te = 50: 50).
The prepared memory element was erased 1000 times and then heat treated at 130 ° C. for 1 hour. Then, the resistance test was performed at room temperature, and the obtained data retention acceleration test was performed. The results are shown in FIGS.
4 to 7 are results showing the relationship between the voltage used for erasing, the erasing resistance (high resistance side), and the recording resistance (low resistance side) before and after the acceleration test for the manufactured memory element. If the voltage at the time of erasing is low as a whole, the erasing is insufficient, and therefore takes an intermediate value between high resistance and low resistance.

In FIG. 4A, the vertical axis represents the logarithmic display of the resistance value (Ω) before the holding acceleration test when the Cu / Te ratio is 2, and the vertical axis in FIG. The logarithmic display of the resistance value (Ω) is shown, and the horizontal axis indicates the erase voltage (V).
Similarly, in FIGS. 5 to 7, the vertical axis of (a) indicates the logarithmic display of the resistance value (Ω) before the holding acceleration test when the Cu / Te ratio is 1.5, 1.27, or 1. The vertical axis of (b) shows the logarithmic display of the resistance value (Ω) after the holding acceleration test, and each horizontal axis shows the erase voltage (V).
4 to 7, the broken line indicates the erasing resistance (high resistance side), and the solid line indicates the recording resistance (low resistance side).

  4 to 7, it can be seen that there is no problem in the recording and erasing operations in the memory elements of any composition before the acceleration test, that is, at the stage where data is set.

Further, when comparing before and after the acceleration test, in the memory element having a Cu / Te ratio of 2 shown in FIG. 4, a phenomenon occurs in which the recording resistance shifts to the high resistance side after the acceleration test, and a recording holding error occurs. I understand that.
On the other hand, in the memory element having a Cu / Te ratio of 1 shown in FIG. 7, the phenomenon that the erase resistance shifts to the low resistance side occurs conversely, and it can be seen that an erase retention error has occurred.

  That is, the balance of the recording / erasing retention characteristics is determined by the Cu / Te ratio of the ion source. Accordingly, there is no problem as a recording / erasing operation, and in order to obtain better holding characteristics, the Cu / Te ratio is preferably set to a composition ratio of 1 to 2 and the Cu / Te ratio is set to 1 to 1.5. It can be seen that the composition ratio of

(Experiment 4)
Next, in the same memory element as in Experimental Example 1, the Ge and Si ratios of the CuTeSiGe film of the ion source layer 3 are changed as shown in Table 2, and the remainder has a Cu / Te ratio of 1.5 (Cu: Te = 3: 2) so as to be a constant ratio.
Next, an acceleration test for recording and holding was performed on the manufactured memory element by the same method as in Experimental Example 3.
Then, with respect to the element after the acceleration test, the gate voltage of the transistor for controlling the recording voltage was changed, and the minimum writing transistor gate voltage at which recording could be held was measured.
Here, it was determined that the change in the element resistance after recording after the acceleration test was less than 50% could be held, and the lowest gate voltage that could be held was used as an index. Then, it was examined how the lowest gate voltage changes depending on the Ge and Si ratio.

FIG. 8 and FIG. 9 show the results of measuring the minimum writing transistor gate voltage at which recording can be held after the acceleration test.
In FIG. 8, the vertical axis represents the minimum write transistor gate voltage (V) at which recording can be held after the acceleration test, and the horizontal axis represents the total ratio of Si element and Ge element in the ion source layer 3 shown in Table 2 ( Atomic%).
In FIG. 9A, the vertical axis represents the minimum writing transistor gate voltage (V) at which recording can be held after the acceleration test, and the horizontal axis represents the ratio of only the Si element in the ion source layer shown in Table 2. (Atom%) is shown. In FIG. 9B, the vertical axis represents the minimum write transistor gate voltage at which recording can be held after the acceleration test, and the horizontal axis represents the ratio of only the Ge element in the ion source layer shown in Table 2.

The minimum writing transistor gate voltage is related to low power consumption, heat generation, ion movement, and the like.
Further, since the current flowing through the element during recording depends on the magnitude of the transistor gate voltage, the current flowing through the element during recording increases as the transistor gate voltage increases. From the viewpoint of low power consumption, it is preferable that the current flowing through the element during recording is low. For this reason, it is desirable that the minimum write transistor gate voltage is also low.

FIG. 8 shows that the minimum write transistor gate voltage increases as the total amount of Ge and Si in the ion source layer increases.
It can be seen that the tendency toward the minimum write transistor gate voltage is better when the total amount of Ge and Si is seen than the amount of only Si and Ge.

  From FIG. 8, it can be seen that the minimum write transistor gate voltage rapidly increases when the total atomic ratio of Ge and Si with respect to the entire ion source layer 3 exceeds 45 atomic%. Therefore, the total atomic ratio of Ge and Si with respect to the entire ion source layer 3 is desirably 0.45 or less.

  The present invention is not limited to the above-described configuration, and various other configurations can be employed without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of the memory element of one embodiment of this invention. It is a schematic block diagram (plan view) of the memory element of FIG. a, b is a measurement result of cumulative frequency distribution of the variable resistance element of Experiment 2. a, b It is the measurement result of the resistance value before and after the holding acceleration test of the resistance change element of Experiment 3. a, b It is the measurement result of the resistance value before and after the holding acceleration test of the resistance change element of Experiment 3. a, b It is the measurement result of the resistance value before and after the holding acceleration test of the resistance change element of Experiment 3. a, b It is the measurement result of the resistance value before and after the holding acceleration test of the resistance change element of Experiment 3. 10 is a measurement result of a minimum write transistor gate voltage of the resistance change element in Experiment 4. FIG. a, b Measurement results of the minimum write transistor gate voltage of the resistance change element in Experiment 4.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Memory layer, 3 Ion source layer, 4 Upper electrode, 10 Resistance change element, 11 Semiconductor substrate, 12 Element isolation layer, 13 Source / drain region, 14 Gate electrode, 15 Plug layer, 16 Metal wiring layer, 17 plug layer, 18 active region, Tr MOS transistor, BL bit line, WL word line, PL plate electrode

Claims (4)

Each of the resistance change elements that reversibly change the resistance value of the memory layer by applying potentials having different polarities to the two electrodes by applying a memory layer between the two electrodes. A memory cell is constructed,
In the plurality of adjacent memory cells, at least a part of the layers including the storage layer of the resistance change element is formed in common by the same layer,
An ion source layer containing one or more metal elements selected from Cu, Ag, and Zn, one or more chalcogen elements selected from Te, S, and Se and Si or Ge on the memory layer. Layered,
The memory element, wherein an atomic composition ratio of the metal element to the chalcogen element is 5 to 0.5.   The memory element according to claim 1, wherein the ion source layer contains both Si and Ge.   The memory element according to claim 2, wherein an atomic composition ratio of the total content of Si and Ge contained in the ion source layer to the entire ion source layer is 0.45 or less. Each of the resistance change elements is configured to have a storage layer between two electrodes, and the resistance value of the recording layer reversibly changes by applying potentials having different polarities to the two electrodes. A memory cell is constructed,
In a plurality of adjacent memory cells, at least a part of the layers including the resistance change element and the storage layer are formed in common by the same layer,
An ion source layer containing one or more metal elements selected from Cu, Ag, and Zn, one or more chalcogen elements selected from Te, S, and Se and Si or Ge on the memory layer. Layered,
A memory element, wherein an atomic composition ratio of the metal element to the chalcogen element is 5 to 0.5;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device comprising a large number of the storage elements.

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