JP4465969B2 - Semiconductor memory element and semiconductor memory device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory element capable of recording information and a semiconductor memory device using the semiconductor memory element.
[0002]
[Prior art]
In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.
[0003]
However, the manufacturing cost of DRAM is higher than that of a general logic circuit LSI or signal processing used in electronic equipment, and thus the manufacturing cost is high.
[0004]
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).
Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
[0005]
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.
[0006]
However, in the above-described nonvolatile memory, it is difficult to secure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.
[0007]
Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. The diffusion changes the electrical characteristics such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).
[0008]
Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Ag, Cu, or Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Ag, Cu, or Zn (see Patent Document 1).
[0009]
In addition, as a method for manufacturing this memory element, an ion conductor made of chalcogenide is deposited on a substrate, and then an electrode containing a metal is deposited on the ion conductor, so that light having an energy larger than the optical gap of the ion conductor is obtained. There has been proposed a method of forming an ionic conductor containing a metal by a method in which a metal is diffused into an ionic conductor to form a solid solution by irradiating or heat.
[0010]
[Patent Document 1]
Special Table 2002-536840 Publication
[Non-Patent Document 1]
Nikkei Electronics 2003.1.20 (page 104)
[0011]
[Problems to be solved by the invention]
However, in the memory element having the above-described configuration, an ionic conductor is formed by a solid solution of chalcogenide and metal, and metal ions, for example, Ag, Cu, Zn, are previously dissolved, thereby diffusing metal ions. A large amount of current is required for recording.
[0012]
Also, the amount of change in resistance value before and after recording is relatively small.
For this reason, when the recorded information is read, it becomes difficult to determine the contents of the information.
[0013]
Furthermore, the manufacturing method in which the metal is diffused into the ionic conductor to be dissolved by irradiating light having energy larger than the optical gap of the ionic conductor or applying heat complicates the manufacturing process.
[0014]
In order to solve the above-described problems, in the present invention, a semiconductor memory element that can easily record and read information and can be easily manufactured by a relatively simple manufacturing method, and a semiconductor using the same A storage device is provided.
[0015]
[Means for Solving the Problems]
The semiconductor memory element of the present invention is configured by sandwiching an amorphous thin film between a first electrode and a second electrode, and the first electrode and the second electrode Only one of the electrodes Contains Ag or Cu, and the amorphous thin film is Does not contain Ag or Cu, Ge and one or more elements selected from S, Se, Te, and Sb By applying a positive voltage so that the electrode side containing Ag or Cu becomes positive, Ag or Cu is ionized from the electrode, diffuses in the amorphous thin film, and the resistance of the amorphous thin film decreases. Therefore, it is possible to record information, and in a state where the information is recorded, by applying a negative voltage so that the electrode side containing Ag or Cu becomes negative, Ag or Cu is ionized to pass through the amorphous thin film. Moves back to the electrode side, the resistance of the amorphous thin film increases, and the recorded information can be erased, and the information is recorded and erased under the condition that the amorphous thin film does not change phase. Is.
[0016]
The semiconductor memory device of the present invention is configured by sandwiching an amorphous thin film between a first electrode and a second electrode, and the first electrode and the second electrode Only one of the electrodes Contains Ag or Cu, and the amorphous thin film is Does not contain Ag or Cu, Ge and one or more elements selected from S, Se, Te, and Sb By applying a positive voltage so that the electrode side containing Ag or Cu becomes positive, Ag or Cu is ionized from the electrode, diffuses in the amorphous thin film, and the resistance of the amorphous thin film decreases. Therefore, it is possible to record information, and in a state where the information is recorded, by applying a negative voltage so that the electrode side containing Ag or Cu becomes negative, Ag or Cu is ionized to pass through the amorphous thin film. Moves back to the electrode side, the resistance of the amorphous thin film increases, and the recorded information can be erased, and the information is recorded and erased under the condition that the amorphous thin film does not change phase. The semiconductor memory element includes a wiring connected to the first electrode side and a wiring connected to the second electrode side, and a large number of semiconductor memory elements are arranged.
[0017]
According to the configuration of the semiconductor memory element of the present invention described above, the amorphous thin film is sandwiched between the first electrode and the second electrode, and the first electrode and the second electrode Only one of the electrodes Contains Ag or Cu, and the amorphous thin film is Does not contain Ag or Cu, By storing Ge or one or more elements selected from S, Se, Te, and Sb, Ag or Cu contained in the electrode is diffused as ions into the amorphous thin film to store information. Is possible.
[0018]
Specifically, when a positive potential is applied to one of the electrodes containing Ag or Cu and a positive voltage is applied to the element, Ag or Cu contained in the electrode is ionized and diffuses into the amorphous thin film. By bonding with electrons at the other electrode side and depositing, the resistance of the amorphous thin film is lowered, and the resistance of the element is also lowered, so that information can be recorded. From this state, when a negative potential is applied to one electrode side containing Ag or Cu and a negative voltage is applied to the element, Ag or Cu deposited on the other electrode side is ionized again, By returning to the electrode side, the resistance of the amorphous thin film returns to the original high state, and the resistance of the element also increases, so that the recorded information can be erased.
[0019]
By configuring the amorphous thin film before recording not to contain ionized Ag or Cu, the current required for recording can be reduced and the resistance change can be increased. Further, the time required for recording can be shortened.
[0020]
According to the configuration of the semiconductor memory device of the present invention described above, the semiconductor memory element of the present invention described above, the wiring connected to the first electrode side, and the wiring connected to the second electrode side are included. By arranging a large number of semiconductor memory elements, it is possible to record information or erase information by passing a current from the wiring to the semiconductor memory elements.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor memory element of the present invention is configured by sandwiching an amorphous thin film between a first electrode and a second electrode, and the first electrode and the second electrode Only one of the electrodes Contains Ag or Cu, and the amorphous thin film is Does not contain Ag or Cu, Ge and one or more elements selected from S, Se, Te, and Sb By applying a positive voltage so that the electrode side containing Ag or Cu becomes positive, Ag or Cu is ionized from the electrode, diffuses in the amorphous thin film, and the resistance of the amorphous thin film decreases. Therefore, it is possible to record information, and in a state where the information is recorded, by applying a negative voltage so that the electrode side containing Ag or Cu becomes negative, Ag or Cu is ionized to pass through the amorphous thin film. Moves back to the electrode side, the resistance of the amorphous thin film increases, and the recorded information can be erased, and the information is recorded and erased under the condition that the amorphous thin film does not change phase. Is.
[0022]
In the semiconductor memory element of the present invention, an electrode layer containing an element having a higher valence when the electrode containing Ag or Cu is ionized than Ag or Cu contained in the electrode. On the opposite side of the amorphous thin film Allows connected configuration.
[0023]
In the semiconductor memory element of the present invention, Electrodes containing Ag or Cu Is an electrode layer made of any one of TiW, Ti, and W. On the opposite side of the amorphous thin film Allows connected configuration.
[0024]
In the semiconductor memory element of the present invention, the amorphous thin film can be configured to include Ge, one or more elements selected from S, Se, Te, and Sb, and Si.
[0025]
FIG. 1 is a schematic configuration diagram (cross-sectional view) of a semiconductor memory element as an embodiment of the present invention.
This semiconductor memory element 10 is doped with a substrate 1 having a high electrical conductivity, for example, a P-type high concentration impurity (P ⁺⁺ The lower electrode 2 is formed on the silicon substrate, and the amorphous thin film 4, the upper electrode 5, the electrode layer 6, A laminated film of conductive layers 7 is formed.
[0026]
For the lower electrode 2, for example, TiW, Ti, W can be used.
When TiW is used for the lower electrode 2, for example, the film thickness may be in the range of 20 nm to 100 nm.
[0027]
The insulating film 3 may be, for example, a hard-cured photoresist or SiO generally used in semiconductor devices. ₂ And Si _Three N _Four Other materials such as SiON, SiOF, Al ₂ O _Three , Ta ₂ O _Five , HfO ₂ , ZrO ₂ Inorganic materials such as fluorinated organic materials, aromatic organic materials, and the like can be used.
[0028]
The amorphous thin film 4 is composed of Ge (germanium) and one or more elements selected from S (sulfur), Se (selenium), Te (tellurium), and Sb (antimony). Among these, S, Se, and Te belong to chalcogenite.
For example, GeSbTe, GeTe, GeSe, GeS, GeSbSe, GeSbS, etc. can be used. These materials have similar electrical and chemical properties to Ag or Cu.
Further, if necessary, the amorphous thin film 4 may contain Si (silicon) or other elements, for example, rare earth elements such as Gd, As, Bi, and the like.
If, for example, GeSbTe is used for the amorphous thin film 4, the film thickness may be in the range of 10 nm to 50 nm, for example.
[0029]
The upper electrode 5 includes Ag or Cu.
For example, the upper electrode 5 can be configured using a film having a composition obtained by adding Ag or Cu to the composition of the amorphous thin film 4, an Ag film, an Ag alloy film, a Cu film, a Cu alloy film, or the like.
When, for example, GeSbTeAg is used for the upper electrode 5, the film thickness may be set to 10 nm to 30 nm, for example. For example, when Ag is used, the film thickness may be 3 nm to 20 nm, for example.
[0030]
The electrode layer 6 connected on the upper electrode 5 is made of a material that does not contain Ag or Cu contained in the upper electrode 5.
The electrode layer 6 is composed of an element having a higher valence when ionized than Ag or Cu contained in the upper electrode 5 (for example, Ti or W used for the lower electrode 2).
For example, TiW, Ti, W or the like used for the lower electrode 2 can be used for the electrode layer 6.
When TiW is used for the electrode layer 6, the film thickness may be set to 20 nm to 100 nm, for example.
[0031]
The conductive layer 7 connects a wiring layer (not shown) and the electrode layer 6 with a low contact resistance.
For example, when TiW is used for the electrode layer 6, it is conceivable to use AlSi for the conductive layer 7.
When AlSi is used for the conductive layer 7, the film thickness may be, for example, 100 nm to 200 nm.
[0032]
A configuration in which the conductive layer 7 also serves as a wiring layer connected to the semiconductor memory element 10 and the wiring layer is directly connected to the electrode layer 6 is also possible.
[0033]
The semiconductor memory element 10 of the present embodiment can store information by operating as follows.
[0034]
First, a positive potential (+ potential) is applied to the upper electrode 5 containing Ag or Cu, and a positive voltage is applied to the semiconductor memory element 10 so that the upper voltage 5 side becomes positive. As a result, Ag or Cu is ionized from the upper electrode 5 and diffuses in the amorphous thin film 4, and is combined with electrons on the lower electrode 2 side and deposited.
Then, Ag or Cu increases in the amorphous thin film 4, and the resistance of the amorphous thin film 4 is lowered. Each layer other than the amorphous thin film 4 originally has a low resistance. Therefore, by reducing the resistance of the amorphous thin film 4, the resistance of the entire semiconductor memory element 10 can also be reduced.
[0035]
Thereafter, when the positive voltage is removed and the voltage applied to the semiconductor memory element 10 is eliminated, the resistance is kept low. This makes it possible to record information.
[0036]
On the other hand, when erasing the recorded information, a negative potential (−potential) is applied to the upper electrode 5 containing Ag or Cu so that the upper electrode 5 side becomes negative. Apply voltage. Thereby, Ag or Cu deposited on the lower electrode 2 side is ionized and moves in the amorphous thin film 4 and returns to the original state on the upper electrode 5 side.
Then, Ag or Cu decreases from within the amorphous thin film 4, and the resistance of the amorphous thin film 4 increases. Each layer other than the amorphous thin film 4 originally has a low resistance. Therefore, by increasing the resistance of the amorphous thin film 4, the resistance of the entire semiconductor memory element 10 can be increased.
After that, when the negative voltage is removed and the voltage applied to the semiconductor memory element 10 is eliminated, the resistance is maintained high. As a result, the recorded information can be erased.
[0037]
By repeating such a process, it is possible to repeatedly record (write) information on the semiconductor memory element 10 and erase the recorded information.
[0038]
For example, when the high resistance state corresponds to the information “0” and the low resistance state corresponds to the information “1”, “0” to “1” in the information recording process by applying a positive voltage. Instead, it can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.
[0039]
In the above-described information recording process and information erasing process, the amorphous thin film 4 remains in an amorphous state and does not change into a crystalline state due to a phase change.
In other words, the amorphous thin film 4 The Information is recorded and erased under a voltage condition that does not cause a phase change.
[0040]
According to the configuration of the semiconductor memory element 10 of the above-described embodiment, the amorphous thin film 4 is composed of Ge and one or more elements selected from S, Se, Te, and Sb, and the upper electrode 5 is composed of Ag or Cu. By containing, it is possible to store information by diffusing and moving Ag or Cu as ions from the upper electrode 5 into the amorphous thin film 4.
Since information is recorded by utilizing the change in resistance of the semiconductor memory element 10, particularly the change in resistance of the amorphous thin film 4, even when the semiconductor memory element 10 is miniaturized, information recording or It becomes easy to hold the recorded information.
[0041]
In addition, since the amorphous thin film 4 does not contain Ag or Cu that becomes ions, Ag or Cu collects in the vicinity of the interface between the upper electrode 5 and the amorphous thin film 4 in a state before recording information or a state where information is erased. In addition, since Ag or Cu hardly diffuses inside the amorphous thin film 4, the resistance of the amorphous thin film 4 can be increased.
Thereby, the resistance of the element 10 can be increased in a state before information is recorded or in a state where the information is erased, and a change in resistance can be increased as compared with a low resistance in a state where information is recorded. .
Therefore, it becomes easy to read and discriminate the recorded information.
[0042]
Furthermore, the current required for recording can be reduced. This is also considered to be because Ag or Cu ions move smoothly because there is no extra Ag or Cu in the amorphous thin film 4. Since the current required for recording can be reduced, power consumption can be reduced.
Further, the time required for recording can be shortened.
[0043]
In addition, according to the semiconductor memory element 10 of the present embodiment, the lower electrode 2, the amorphous thin film 4, the upper electrode 5, the electrode layer 6, and the conductive layer 7 can all be made of a material that can be sputtered. Become. Sputtering may be performed using a target having a composition suitable for the material of each layer.
This eliminates the need for a special process (a process of diffusing metal from the electrode) such as heat treatment or light irradiation at a high temperature.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.
That is, it is possible to manufacture a semiconductor memory element by a material and a manufacturing method used in a normal MOS logic circuit manufacturing process (film formation by sputtering of electrode material, normal etching process such as plasma or RIE). .
Therefore, the semiconductor memory element 10 can be easily manufactured by a relatively simple method.
[0044]
The semiconductor memory element 10 of FIG. 1 can be manufactured as follows, for example.
First, a lower electrode 2 such as a TiW film is deposited on a substrate 1 having a high electrical conductivity, such as a silicon substrate doped with a high concentration of P-type impurities.
Next, an insulating film 3 is formed so as to cover the lower electrode 2, and then an opening is formed in the insulating film 3 on the lower electrode 2.
[0045]
Next, the oxidized surface of the lower electrode 2 is etched to remove the thin oxide film and obtain an electrically good surface.
Thereafter, an amorphous thin film 4 such as a GeSbTe film is formed by, for example, a magnetron sputtering apparatus.
Next, the upper electrode 5 such as a GeSbTeAg film or an Ag film is formed by a magnetron sputtering apparatus, for example.
Subsequently, an electrode layer 6 such as a TiW film is formed by a magnetron sputtering apparatus, for example, and a conductive layer 7 such as an AlSi film or a Cu film is further formed.
[0046]
The amorphous thin film 4, the upper electrode 5, the electrode layer 6, and the conductive layer 7 can be replaced by changing the sputtering target while keeping the same vacuum state by using the same magnetron sputtering apparatus if materials are selected. Thus, it is possible to continuously form a film.
[0047]
Thereafter, the amorphous thin film 4, the upper electrode 5, the electrode layer 6, and the conductive layer 7 are patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
[0048]
In this way, the semiconductor memory element 10 shown in FIG. 1 can be manufactured.
[0049]
In the semiconductor memory element 10 of the above-described embodiment, the upper electrode 5 includes Ag or Cu and the lower electrode 2 does not include, but only the lower electrode includes Ag or Cu. Configuration and May be.
When the lower electrode includes Ag or Cu, an electrode layer corresponding to the electrode layer 6 in FIG. 1 (consisting of an element having a higher valence when ionized than Ag or Cu) is provided between the lower electrode and the substrate. Is preferably provided.
[0050]
A semiconductor memory device (semiconductor memory device) can be configured by arranging a large number of the semiconductor memory elements 10 of the above-described embodiment in a matrix.
For each semiconductor memory element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 5 side are provided. For example, each semiconductor memory element 10 is arranged near the intersection of these wirings. What should I do?
[0051]
Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the conductive layer 7 is formed in common in the memory cell in the column direction, and a potential is applied. A memory cell to be recorded is selected by selecting the lower electrode 2 and the wiring through which a current flows, and a current is passed through the semiconductor memory element 10 of this memory cell to record information and erase the recorded information. It can be carried out.
[0052]
The semiconductor memory element 10 according to the above-described embodiment can easily record information and read information, reduce power consumption, and shorten the time required for recording. Therefore, by configuring the semiconductor memory device using the semiconductor memory element 10, information can be easily recorded and read out, and the power consumption of the entire semiconductor memory device can be reduced and the semiconductor memory device can operate at high speed. A semiconductor memory device can be configured.
Further, even when the semiconductor memory element 10 of the above-described embodiment is miniaturized, it becomes easy to record information and hold the recorded information. Miniaturization can be achieved.
Furthermore, since the semiconductor memory element 10 of the above-described embodiment can be easily manufactured by a simple method, the manufacturing cost of the semiconductor memory device can be reduced and the manufacturing yield structure can be achieved.
[0053]
(Example)
Next, the semiconductor memory element 10 of the above-described embodiment was actually manufactured and the characteristics were examined.
[0054]
<Experiment 1>
First, a TiW film having a thickness of 100 nm was deposited as a lower electrode 2 on a substrate 1 having high electrical conductivity, for example, a silicon substrate doped with a high concentration of P-type impurities by sputtering.
Next, a photoresist was formed to cover the lower electrode 2, and then exposure and development were performed by photolithography to form an opening (through hole) in the photoresist on the lower electrode 2. The size of the opening (through hole) was 2 μm in length and 2 μm in width.
Thereafter, annealing was performed in vacuum at 270 ° C. to alter the photoresist, and the insulating film 3 was formed as a hard-cure resist that is stable with respect to temperature and etching. The reason why the hard-cure resist is used for the insulating film 3 is that it can be easily formed experimentally, and in the case of manufacturing a product, another material (silicon oxide film or the like) is used for the insulating film 3. May be good.
Thereafter, the surface of the lower electrode 2 exposed by the through hole was etched to remove the thin oxide film and obtain an electrically good surface.
Subsequently, a GeSbTe film having a thickness of 25 nm was formed as the amorphous thin film 4 by a magnetron sputtering apparatus. The composition of this GeSbTe film is Ge _{twenty two} Sb _{twenty two} Te ₅₆ (Subscript is atomic%).
Further, in the same magnetron sputtering apparatus, a GeSbTeAg film having a thickness of 25 nm was formed as the upper electrode 5 while maintaining the same vacuum. The composition of this GeSbTeAg film is (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₄₁ Ag ₅₉ (Subscript is atomic%).
Further, in the same magnetron sputtering apparatus, a TiW film having a thickness of 100 nm was formed as the electrode layer 6 while maintaining the same vacuum, and subsequently an AlSi film having a thickness of 100 nm was formed as the conductive layer 7. . The composition of the TiW film and AlSi film is Ti, respectively. ₅₀ W ₅₀ And Al ₉₇ Si _Three (Subscript is atomic%).
Thereafter, each layer of the amorphous thin film 4, the upper electrode 5, the electrode layer 6, and the conductive layer 7 deposited on the insulating film 3 made of a hard-cure resist using a plasma etching apparatus by photolithography is 50 μm × 50 μm in size. Then, patterning was performed.
In this way, the semiconductor memory element 10 having the structure shown in FIG.
[0055]
A positive potential (+ potential) was applied to the conductive layer 7 on the upper electrode 5 side of the semiconductor memory element 10 of the sample 1, and the back side of the substrate 1 was connected to the ground potential (ground potential).
Then, the positive potential applied to the conductive layer 7 was increased from 0 V, and the change in current was measured. However, the current limiter was set to operate when the current reached 0.5 mA, and the positive potential applied to the conductive layer 7, that is, the voltage applied to the element 10 was not increased beyond that.
Further, from the state where the current reached 0.5 mA and the current limiter was operated, the positive potential applied to the conductive layer 7 was decreased to 0 V, and the change in current was measured.
The obtained IV characteristic graph is shown in FIG. 2A.
[0056]
As shown in FIG. 2A, the resistance is initially high, the semiconductor memory element 10 is in the OFF state, and when the voltage increases, the current increases rapidly at a certain threshold voltage Vth or higher, that is, the resistance decreases and the ON state is reached. It can be seen that the transition occurs. Thereby, it is understood that information is recorded.
On the other hand, by decreasing the voltage, the current also decreases. However, the decrease in current is larger and the resistance gradually increases, but eventually the resistance value is sufficiently lower than the initial resistance value. It can be seen that the ON state is maintained and the recorded information is retained.
In the case of this sample 1, the resistance value at the voltage V = 0.1 V was about 2 MΩ in the OFF state and about 1 kΩ in the ON state.
[0057]
Although not shown in the characteristic diagram of FIG. 2A, a reverse polarity voltage V, that is, a negative potential (−potential) is applied to the conductive layer 7 on the upper electrode 5 side, and the back side of the substrate 1 is grounded (ground potential). After applying a negative potential of V = −1V to the conductive layer 7 and connecting the electrode to the conductive layer 7, it is confirmed that the resistance returns to the high resistance state of the initial OFF state by setting the potential of the conductive layer 7 to 0V. It was. That is, it can be seen that the information recorded in the semiconductor memory element 10 can be erased by applying a negative voltage.
[0058]
<Experiment 2>
Ag was added to GeSbTe of the amorphous thin film 4, and the characteristics were examined.
First, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₈₁ Ag ₁₉ A GeSbTeAg film having a composition (subscript is atomic%, the same shall apply hereinafter) was formed, and the others were prepared in the same manner as Sample 1, and a semiconductor memory element was prepared as Sample 2.
Next, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₇₀ Ag ₃₀ A GeSbTeAg film having the following composition was formed, and a semiconductor memory element was prepared in the same manner as in Sample 1 except that it was designated as Sample 3.
Next, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₅₈ Ag ₄₂ A GeSbTeAg film having the following composition was formed, and a semiconductor memory element was prepared in the same manner as in Sample 1 except that the sample 4 was obtained.
[0059]
The IV characteristics of the semiconductor memory elements of Sample 2 to Sample 4 were measured. The measurement result of sample 2 is shown in FIG. 2B, the measurement result of sample 3 is shown in FIG. 3C, and the measurement result of sample 4 is shown in FIG. 3D.
As shown in FIGS. 2B, 3C, and 3D, the silver Ag content increases, the threshold voltage Vth when the voltage is increased, and the I− after the threshold voltage Vth is exceeded. It can be seen that the slope of V dI / dV, that is, the rate of change in resistance becomes moderate.
This is because, for example, the mechanism of changing resistance is that a thin current path having a high Ag concentration and a low resistance is formed locally as the electric field of Ag ions contained in the upper electrode 5 moves to the negative electrode side. Assuming that Ag is added to GeSbTe, the voltage at which the current path is formed becomes slightly higher, and the speed of forming the current path is slow, or the variation in the voltage at which multiple current paths are formed becomes large. It can be considered because of this.
3C and 3D, that is, sample 3 and sample 4, when the current limiter is 0.5 mA, when the current is returned to 0 V, the resistance value also returns to the original value, and recording cannot be maintained. Therefore, the result of measurement with the current limiter value set to 1 mA is shown.
Further, the ratio of the resistance change before and after recording was 400 times in the sample 1 in FIG. 2A, 80 times in the sample 2 in FIG. 2B, and 7 times in the sample 3 in FIG. 3C and the sample 4 in FIG. 3D. It became.
That is, when a voltage higher than the threshold voltage is applied during recording, each sample has a relatively small resistance, but the rate at which the resistance increases again as the applied voltage is decreased. It can be seen that the rate of resistance change is reduced due to the above.
That is, it is presumed that it becomes difficult to maintain the recorded ON state as the Ag content increases.
[0060]
From the above results, including Ag in the GeSbTe of the amorphous thin film 4 in advance causes an increase in recording voltage and recording current, thereby causing either a variation in recording voltage or a decrease in recording speed. Furthermore, it has been found that there is a problem that the ratio of the resistance change amount decreases, that is, the signal level decreases when the recording is read, and the retention characteristic of the recording data is weakened.
Therefore, it is desirable to manufacture the semiconductor memory element 10 so that the amorphous thin film 4 does not contain Ag or Cu contained in the upper electrode 5.
[0061]
<Experiment 3>
Next, the Ge content of the GeSbTe film of the amorphous thin film 4 was changed and the characteristics were examined.
First, as the lower electrode 2 and the electrode layer 6, instead of the TiW film, a Ti film was formed with a film thickness of 100 nm, and the others were manufactured in the same manner as the sample 1, and a semiconductor memory element was prepared as a sample 5.
Next, as the amorphous thin film 4, Ge ₃₁ Sb ₁₉ Te ₅₀ A GeSbTe film having the composition (subscript is atomic%, the same shall apply hereinafter) was formed, and the others were fabricated in the same manner as Sample 5 to prepare a semiconductor memory element as Sample 6.
Next, as the amorphous thin film 4, Ge ₃₈ Sb ₁₇ Te ₄₅ A GeSbTe film of the composition was formed, and a semiconductor memory element was fabricated in the same manner as in Sample 5 except that it was designated as Sample 7.
Next, as the amorphous thin film 4, Ge ₄₉ Sb ₁₅ Te ₃₇ A GeSbTe film of the composition was formed, and the others were the same as in Sample 5, and a semiconductor memory element was manufactured as Sample 8.
[0062]
The IV characteristics of the semiconductor memory elements of Sample 5 to Sample 8 were measured. The measurement result of the sample 5 is shown in FIG. 4A, the measurement result of the sample 6 is shown in FIG. 4B, the measurement result of the sample 7 is shown in FIG. 5C, and the measurement result of the sample 8 is shown in FIG.
As shown in FIGS. 4A to 5D, it was confirmed that recording and record holding can be performed correctly in these wide Ge composition ranges.
5C and 5D, it can be seen that as the Ge content increases, dI / dV when a voltage equal to or higher than the threshold voltage is applied becomes moderate. Considering the recording characteristics of the memory, the smaller the Ge content, the easier the recording. However, increasing the Ge content has the advantage of improving the thermal stability of the semiconductor memory element. Therefore, the Ge content may be controlled according to the required characteristics.
[0063]
<Experiment 4>
Next, the material of the lower electrode 2 and the electrode layer 6 was changed and the characteristics were examined.
As the lower electrode 2 and the electrode layer 6, instead of the TiW film, a W film was formed with a film thickness of 100 nm.
The IV characteristic of the semiconductor memory element of Sample 9 was measured. The measurement results are shown in FIG.
As can be seen from FIG. 6, good IV characteristics can be obtained and recording can be performed easily, as in FIG. 2A and the like.
[0064]
Further, the lower electrode 2 and the electrode layer 6 are made of Ti ₅₀ W ₅₀ The sample was changed to a TiW film having a composition other than that, a Ti / TiW laminated film, a TiW / Ti laminated film, a TiW / W laminated film, and a W / TiW laminated film. As with 1 etc., good IV characteristics were obtained.
Further, when the conductive layer 7 was replaced with a Cu film, when a sample was similarly prepared and measured, good IV characteristics were obtained as in the case of the sample 1 and the like.
[0065]
<Experiment 5>
Next, as the upper electrode 5 containing Ag, the characteristics were examined using an Ag film instead of the GeSbTeAg film.
As the upper electrode 5, an Ag film having a film thickness of 6 nm was formed instead of the GeSbTeAg film, and a semiconductor memory element was fabricated in the same manner as in the sample 1, and a sample 10 was obtained.
The IV characteristics of the semiconductor memory element of Sample 10 were measured. The measurement results are shown in FIG.
From FIG. 7, it can be seen that, as in FIG. 2A and the like, good IV characteristics can be obtained and recording can be performed easily. In particular, it can be seen that dI / dV during recording is very steep compared to FIG. 2A.
Then, considering the results of FIG. 7 and the results of FIGS. 2A to 3D, there is a difference between the concentration of Ag and Cu contained in the upper electrode 5 and the concentration of Ag and Cu contained in the amorphous thin film 4. It can be seen that the larger the value, the steep dI / dV during recording, and the better recording characteristics can be obtained.
[0066]
A sample was prepared by changing the film thickness of the Ag film, and the same measurement was performed. As a result, if the film thickness was 3 nm or more, substantially similar IV characteristics were obtained.
[0067]
<Experiment 6>
The amorphous thin film 4 was doped with an impurity metal different from ion or Ag or Cu, specifically Gd, which is a rare earth metal, and the characteristics were examined.
First, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₈₉ Gd ₁₁ A GeSbTeGd film having a composition (subscript is atomic%, the same shall apply hereinafter) was formed, and the others were prepared in the same manner as Sample 1 to prepare a semiconductor memory element as Sample 11.
Next, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₈₂ Gd ₁₈ A GeSbTeGd film of the composition was formed, and the others were the same as in Sample 1, and a semiconductor memory element was manufactured as Sample 12.
The IV characteristics of the semiconductor memory elements of Sample 11 and Sample 12 were measured. The measurement result of the sample 11 is shown in FIG. 8A, and the measurement result of the sample 12 is shown in FIG. 8B.
As shown in FIG. 8A and FIG. 8B, it was confirmed that in this case as well, recording and record holding can be performed correctly.
Further, the addition of the rare earth element Gd increases the resistance value before recording, becomes 1 MΩ or more, and has an effect that the resistance value is stable even after a high temperature has passed. In any of the 12 samples, the resistance value hardly changed after annealing at 270 ° C. for 1 hour.
That is, it is presumed that the addition of rare earth elements raises the crystallization temperature and keeps the amorphous state stable.
Further, the addition of rare earth elements increases the threshold voltage, which is effective when, for example, it is desired to set a high voltage during reproduction (reading).
Since rare earth elements have the same outermost electronic structure, they have electrically equivalent characteristics regardless of the elements. Therefore, not only Gd but also La, Ce, Pr, Nd, Sm, Eu, Tb, Dy. The same effect can be expected by using any element of, Ho, Er.
[0068]
<Experiment 7>
Impurity elements, specifically Si, were added to the amorphous thin film 4 to investigate the characteristics.
First, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₉₃ Si ₇ A GeSbTeSi film having a composition (subscript is atomic%, the same shall apply hereinafter) was formed, and a semiconductor memory element was prepared in the same manner as in Sample 1 to obtain Sample 13.
Next, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₈₅ Si ₁₅ A GeSbTeSi film of the composition was formed, and the others were the same as in Sample 1, and a semiconductor memory element was produced as Sample 14.
Next, as the amorphous thin film 4, (Ge _{twenty two} Sb _{twenty two} Te ₅₆ ) ₇₇ Si _{twenty three} A GeSbTeSi film of the composition was formed, and the others were the same as in Sample 1, and a semiconductor memory element was manufactured as Sample 15.
The IV characteristics of the semiconductor memory elements of Sample 13 to Sample 15 were measured. The measurement result of the sample 13 is shown in FIG. 9A, the measurement result of the sample 14 is shown in FIG. 9B, and the measurement result of the sample 15 is shown in FIG. 9C.
From FIG. 9A and FIG. 9B, it was confirmed that the I-V characteristics hardly changed and the recording and the retention of the recording could be correctly performed until the addition amount of Si was about 15 atomic% or less.
On the other hand, as shown in FIG. 9C, when the addition amount of Si is 23 atomic%, the threshold voltage increases and recording at 0.5 mA becomes difficult, and a current of about 1 mA is required.
In addition, it can be expected that thermal stability is increased by adding Si to GeSbTe of the amorphous thin film 4. This is because the covalent bond energy of Si—Si is high, so the melting point of Si alone is high, and the higher the Si composition in the Si—Ge alloy composition, the higher the melting point. Therefore, even when Si is added to GeSbTe. Similarly, due to the addition of Si, the covalent bond is increased, and the melting point and the crystallization temperature are expected to increase.
[0069]
<Experiment 8>
The characteristics of the amorphous thin film 4 were examined by changing the film thickness.
First, a semiconductor memory element was prepared as Sample 16 in the same manner as Sample 1 except that the lower electrode 2 was a Ti film having a thickness of 20 nm, the GeSbTe film of the amorphous thin film 4 was 14 nm.
Next, the thickness of the GeSbTe film of the amorphous thin film 4 was set to 25 nm, and a semiconductor memory element was fabricated in the same manner as the sample 16 except that the sample 17 was obtained.
In this sample 17, the thickness of the GeSbTe film of the amorphous thin film 4 is the same as that of the sample 1.
Next, the thickness of the GeSbTe film of the amorphous thin film 4 was set to 38 nm, and a semiconductor memory element was fabricated in the same manner as the sample 16 except that the sample 18 was obtained.
Next, the thickness of the GeSbTe film of the amorphous thin film 4 was set to 51 nm, and a semiconductor memory element was fabricated in the same manner as the sample 16 except that the sample 19 was obtained.
[0070]
The IV characteristics of the semiconductor memory elements of Sample 16 to Sample 19 were measured. The measurement result of the sample 16 is shown in FIG. 10A, the measurement result of the sample 17 is shown in FIG. 10B, the measurement result of the sample 18 is shown in FIG. 11C, and the measurement result of the sample 19 is shown in FIG.
As shown in FIGS. 10A to 11D, it was confirmed that recording and record holding can be performed correctly in these wide film thickness ranges.
In the thinnest sample 16 (FIG. 10A), the threshold voltage is as low as about 0.1V, but the threshold voltage does not change so much depending on the film thickness in other samples, and both are about 0.17V. It has become.
[0071]
In the semiconductor memory element 10 of the above-described embodiment, a ground potential (ground potential) is applied to the back side of the substrate 1 using a silicon substrate having a high conductivity and high conductivity as the substrate 1. Other configurations are possible for applying a voltage to the side.
For example, an electrode formed on the surface of the substrate and electrically insulated from the silicon substrate may be used.
Further, a semiconductor substrate other than silicon or an insulating substrate such as a substrate made of glass or resin may be used as the substrate.
[0072]
A semiconductor memory device (semiconductor memory device) can be formed by arranging a large number of semiconductor memory elements, for example, in a column shape or a matrix shape, using the semiconductor memory element of the present invention.
In addition, a memory cell is configured by connecting a MOS transistor or a diode for selecting an element to each semiconductor memory element as necessary.
Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.
[0073]
The semiconductor memory element of the present invention can be applied to various semiconductor memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed Any memory form can be applied.
[0074]
The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.
[0075]
【The invention's effect】
According to the above-described present invention, it is possible to reduce the current required for recording in the semiconductor memory element and increase the resistance change of the element before and after recording.
Thereby, power consumption when recording information on the element can be reduced, and information can be easily read.
Also, the time required for recording can be shortened.
[0076]
Furthermore, since information is recorded by utilizing changes in the resistance of the element, especially the resistance of the amorphous thin film, even when the element is miniaturized, it is easy to record information and hold the recorded information. Has the advantage of becoming.
[0077]
Therefore, according to the present invention, information recording and information reading can be easily performed, power consumption is reduced, and a semiconductor memory device that operates at high speed can be configured. Further, integration (high density) and miniaturization of the semiconductor memory device can be achieved.
[0078]
Furthermore, the semiconductor memory element of the present invention can be manufactured by materials and manufacturing methods used in a normal MOS logic circuit manufacturing process, that is, no special steps such as high-temperature heat treatment and light irradiation are required. It becomes possible to manufacture with.
That is, a semiconductor memory element can be easily manufactured by a relatively simple method.
Therefore, according to the present invention, a semiconductor memory element and a semiconductor memory device can be manufactured at a low cost, and an inexpensive semiconductor memory device can be provided. It is also possible to improve the manufacturing yield of the semiconductor memory device.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a semiconductor memory element of the present invention.
FIG. 2A is a diagram showing measurement results of IV characteristics of a sample of the semiconductor memory element of FIG. B is a diagram showing measurement results of IV characteristics of a sample obtained by adding Ag to an amorphous thin film.
FIGS. 3A and 3B are diagrams showing measurement results of IV characteristics of a sample in which Ag is added to an amorphous thin film. FIGS.
FIGS. 4A and 4B are diagrams showing measurement results of IV characteristics of samples in which the Ge content of an amorphous thin film is changed.
FIGS. 5A and 5B are diagrams showing measurement results of IV characteristics of a sample in which the Ge content of an amorphous thin film is changed.
FIG. 6 is a diagram showing measurement results of IV characteristics of a sample using W for the lower electrode and the electrode layer.
FIG. 7 is a diagram showing measurement results of IV characteristics of a sample in which an amorphous thin film is an Ag film.
FIGS. 8A and 8B are diagrams showing measurement results of IV characteristics of a sample in which Gd is added to an amorphous thin film. FIGS.
FIGS. 9A to 9C are diagrams showing measurement results of IV characteristics of a sample obtained by adding Si to an amorphous thin film. FIGS.
FIGS. 10A and 10B are diagrams illustrating measurement results of IV characteristics of samples in which the thickness of the GeSbTe film, which is an amorphous thin film, is changed. FIGS.
FIGS. 11A and 11B are diagrams showing measurement results of IV characteristics of a sample in which the thickness of a GeSbTe film as an amorphous thin film is changed. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower electrode, 4 Amorphous thin film, 5 Upper electrode, 6 Electrode layer, 7 Conductive layer, 10 Semiconductor memory element

Claims (8)

An amorphous thin film is sandwiched between the first electrode and the second electrode,
Only one of the first electrode and the second electrode contains Ag or Cu,
The amorphous thin film does not contain Ag or Cu, and consists of Ge and one or more elements selected from S, Se, Te, and Sb.
By applying a positive voltage so that the electrode side containing Ag or Cu is positive, Ag or Cu is ionized from the electrode, diffuses in the amorphous thin film, and the resistance of the amorphous thin film is low. So you can record information,
In a state where information is recorded, by applying a negative voltage so that the electrode side containing Ag or Cu becomes negative, Ag or Cu is ionized and moves in the amorphous thin film and returns to the electrode side. , The resistance of the amorphous thin film is increased, the recorded information can be erased,
Information is recorded and erased under conditions such that the amorphous thin film does not change phase.   The electrode containing Ag or Cu is connected to an electrode layer made of an element having a higher valence when ionized than Ag or Cu contained in the electrode on the side opposite to the amorphous thin film. The semiconductor memory element as described. The semiconductor memory element according to claim 1, wherein an electrode containing Ag or Cu is connected to an electrode layer made of any one of TiW, Ti, and W on the side opposite to the amorphous thin film .   The semiconductor memory element according to claim 1, wherein the amorphous thin film is made of Ge, one or more elements selected from S, Se, Te, and Sb, and Si. An amorphous thin film is sandwiched between the first electrode and the second electrode, and only one of the first electrode and the second electrode contains Ag or Cu. A positive voltage is applied so that the electrode side containing Ag or Cu is positive, and does not contain Ag or Cu, is composed of Ge and one or more elements selected from S, Se, Te, and Sb. As a result, Ag or Cu is ionized from the electrode and diffuses in the amorphous thin film, so that the resistance of the amorphous thin film is lowered, so that information can be recorded. By applying a negative voltage so that the electrode side containing N is negative, Ag or Cu is ionized, moves in the amorphous thin film, returns to the electrode side, and the amorphous thin film Resistance becomes high, and it is possible to erase the recorded information, under conditions such that the amorphous thin film does not change phase, the semiconductor memory device recording and erasing of information is performed,
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A semiconductor memory device comprising a large number of the semiconductor memory elements.   An electrode containing Ag or Cu of the semiconductor memory element is connected to an electrode layer made of an element having a higher valence when ionized than Ag or Cu contained in the electrode on the side opposite to the amorphous thin film. The semiconductor memory device according to claim 5. The semiconductor memory device according to claim 5, wherein an electrode containing Ag or Cu of the semiconductor memory element is connected to an electrode layer made of any one of TiW, Ti, and W on the side opposite to the amorphous thin film .   6. The semiconductor memory device according to claim 5, wherein the amorphous thin film of the semiconductor memory element is made of Ge, one or more elements selected from S, Se, Te, and Sb, and Si.

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