JP4848633B2 - Storage element and storage device - Google Patents

Storage element and storage device Download PDF

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JP4848633B2
JP4848633B2 JP2004361755A JP2004361755A JP4848633B2 JP 4848633 B2 JP4848633 B2 JP 4848633B2 JP 2004361755 A JP2004361755 A JP 2004361755A JP 2004361755 A JP2004361755 A JP 2004361755A JP 4848633 B2 JP4848633 B2 JP 4848633B2
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memory
thin film
oxide
memory element
layer
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JP2006173267A (en
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徹也 水口
彰 河内山
勝久 荒谷
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ソニー株式会社
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/08Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H01L45/085Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/1253Electrodes
    • H01L45/1266Electrodes adapted for supplying ionic species
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
    • H01L45/146Binary metal oxides, e.g. TaOx
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • H01L45/1625Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30Resistive cell, memory material aspects
    • G11C2213/31Material having complex metal oxide, e.g. perovskite structure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50Resistive cell structure aspects
    • G11C2213/56Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

Furthermore, various non-volatile memories using a crystalline oxide material have also been proposed. For example, a Cr-doped SrZrO 3 crystal material is sandwiched between a lower electrode made of SrRuO 3 or Pt and an upper electrode made of Au or Pt. In a device having a structure, there has been reported a memory in which resistance is reversibly changed by application of voltages having different polarities (see Non-Patent Document 2). However, the details such as the principle are unknown.
Special Table 2002-536840 Publication Nikkei Electronics January 20, 2003 issue (page 104) A. Beck et al., Appl. Phys. Lett., 77, (2000), p. 139

  However, the above-described memory element having a structure in which either the upper electrode or the lower electrode contains Cu, Ag, Zn and GeS or GeSe amorphous chalcogenide material is sandwiched between these electrodes, or memory using a crystalline oxide material The element has a very large resistance on / off ratio, that is, a ratio of a resistance value in a low resistance state (on resistance) to a resistance value in a high resistance state (off resistance), for example, four or more digits.

When a short voltage pulse is applied to a memory element having a very large resistance on / off ratio, an intermediate value of these resistance values may be obtained.
If the resistance value of the memory element takes an intermediate value, the data identification margin decreases at the time of reading.

The problem that the resistance value takes an intermediate value is that the film thickness of a thin film with variable resistance, for example, GeS, GeSe, etc. is relatively thick (for example, 10 nm or more). For this reason, it is considered that the result is that atoms such as Cu, Ag, and Zn that should move as ions do not move between certain positions but are trapped in the middle. In addition, since the thickness of the thin film whose resistance changes is relatively large, the operation speed of the memory element is reduced.
Furthermore, since the electric field strength during recording / erasing operation is weakened, the energy level at which ion atoms after movement (transition from the ionic state to the non-ionic state after the recording or erasing process) resumes moving. As a result, it is difficult to sufficiently secure the retention characteristics necessary for the nonvolatile memory.

Therefore, in the memory element described above, it is desirable to use a material having a sufficient withstand voltage even in a thin film thickness for a memory thin film in which information is recorded by changing resistance.
Furthermore, when the memory thin film has a low resistance, a current having a relatively large current density flows and becomes relatively high due to Joule heat. Therefore, it is desirable to use a material having a high melting point.

Therefore, the present inventors have previously proposed to use a rare earth oxide thin film as a memory thin film in which information is recorded by changing resistance.
By using a rare earth oxide thin film as the memory thin film, a sufficient resistance change can be obtained even if the film thickness is reduced. Therefore, the above-mentioned problems can be solved by reducing the film thickness and increasing the electric field strength. Is possible.

Various rare earth oxides can be used as the material for the rare earth oxide thin film, but considering the reduction of the cost of the material, a wider range of materials can be used including those other than the rare earth oxide. Is desirable.
In particular, when a memory element manufacturing process is incorporated in a semiconductor manufacturing process, for example, a material that has been used in a semiconductor manufacturing process or a material that has been studied for adaptability to a semiconductor. There is an advantage that it is preferable to use.

  In order to solve the above-described problems, the present invention provides a storage element that can stably perform operations such as information recording and that is stable against heat, and a storage device using the storage element. Is.

The memory element of the present invention is configured by sandwiching a memory layer and an ion source layer between a first electrode and a second electrode, the ion source layer includes CuTe, and the memory layer is made of tantalum oxide. , Niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixture thereof.

The memory device of the present invention is configured by sandwiching a memory layer and an ion source layer between a first electrode and a second electrode, the ion source layer includes CuTe, and the memory layer is made of tantalum oxide. Element, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixed material thereof, a wiring connected to the first electrode side, and a second electrode side And a plurality of memory elements are arranged.

According to the configuration of the memory element of the present invention described above, the memory layer and the ion source layer are sandwiched between the first electrode and the second electrode, and the ion source layer includes CuTe . Information can be recorded by utilizing the change in the resistance state of the memory layer.

Specifically, for example, when a positive potential is applied to the ion source layer itself containing CuTe or the electrode side in contact with the ion source layer to apply a voltage to the memory element, Cu (ion source element) contained in the ion source layer Is ionized and diffused in the memory layer and combined with electrons in the other electrode side and deposited, or by staying in the memory layer and forming an impurity level of the insulating film, The resistance value is lowered, which makes it possible to record information.
From this state, when a negative potential is applied to the ion source layer containing CuTe or one electrode in contact with the ion source layer and a negative voltage is applied to the memory element, Cu deposited on the other electrode side is again removed. By ionizing and returning to one electrode side, the resistance value of the memory layer returns to the original high state, and the resistance value of the memory element also increases, so that the recorded information can be erased.

Further, since Te (chalcogenide element) is contained in the ion source layer, the ionization of Cu is promoted.

Since the storage layer is made of any one of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixed material thereof, the melting point of these oxides is high. It is possible to stabilize the microstructure of the memory layer against the rise.
As a result, the heat resistance of the memory layer can be improved, so that the production yield of the memory element under a high temperature process can be improved, and the local temperature rise during the operation of the memory element such as recording / erasing can be improved. The stability can be improved, for example, the number of times of rewriting can be increased, and further, a high resistance state can be stably maintained even during long-term data storage in a high temperature environment or the like.
In addition, since the memory layer made of the above oxide has sufficient withstand voltage even when the film thickness is reduced, a high resistance state can be easily realized and defects such as pinholes can be reduced. Therefore, information recording can be performed stably.

  According to the configuration of the memory device of the present invention described above, the memory element according to the present invention described above, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, Since a large number of memory elements are arranged, information can be recorded and information can be erased by supplying current from the wiring to the memory elements.

Oite the aforementioned memory element and memory device of the present invention, by the ion source layer comprises a CuTe, Te is high conductivity as compared with other chalcogen element, also Cu since even high conductivity The resistance value of the ion source layer is lowered, and the difference in resistance value with the memory layer is increased. For this reason, the resistance change of the memory element due to the recording / erasing of information is mainly due to the resistance change of the memory layer having a high resistance value.
As a result, even if the resistance value of the ion source layer included in CuTe changes due to a temperature rise, the change in the resistance value of the memory element is hardly affected, so that the memory operation is not greatly affected.
Accordingly, it is possible to further suppress the deterioration of the characteristics of the memory element during manufacturing, use, or storage in a high temperature environment.

  According to the present invention described above, since the high resistance state can be stably maintained even when the storage element is used in a high temperature environment or when long-term data is stored, the information recorded in the storage layer can be stabilized. Thus, the reliability of the memory element can be increased.

  Furthermore, since information is recorded by utilizing a change in the resistance value of the memory element, in particular, a change in the resistance value of the memory layer, even when the memory element is miniaturized, the information is recorded or recorded information. It has the advantage that the holding | maintenance of becomes easy.

Therefore, according to the present invention, a highly reliable storage device can be configured.
In addition, the storage device can be highly integrated (densified) and downsized.

  First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.

  In the memory element described above, the thin film (memory thin film) that becomes a recording layer on which information is recorded by changing the resistance can easily realize a high resistance state and has fewer defects such as pinholes. Thus, it is desirable that sufficient insulation resistance can be obtained even though the film is very thin. In the low resistance state (ON state), a relatively large current density of current flows and Joule heat is generated, and the operation is performed in a considerably high temperature state. Therefore, a material having a high melting point from the viewpoint of stable operation even at a high temperature. It is desirable that

Examples of materials for which sufficient insulation resistance is obtained with a thin film and whose adaptability to semiconductors has been studied include oxide film materials for gate insulating films of MOS transistors and oxide films for capacitors of DRAMs.
As the insulating film, SiO 2 is generally used. In addition, a hafnium oxide film, a tantalum oxide film, an aluminum oxide film, or the like is used for thinning the gate oxide film or increasing the capacitance. Various new materials have been studied.

Therefore, in the present invention, any of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixed material thereof is used for the memory layer of the memory element.
Accordingly, a sufficient insulation system can be obtained even with a very thin film, and since the melting point of these oxides is relatively high, the memory element can be stably operated even at a high temperature.

  These tantalum oxides, niobium oxides, aluminum oxides, hafnium oxides, and zirconium oxides are used in semiconductor processes as described above, or are commonly used, so they are relatively available. It has the advantage of being easy and inexpensive.

  Subsequently, specific embodiments of the present invention will be described.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element is shown in FIG.
In this memory element 10, a lower electrode 2 is formed on a substrate 1 having a high electrical conductivity, for example, a P-type high concentration impurity doped (P ++ ) silicon substrate 1, and a Cu electrode is formed on the lower electrode 2. , Ag, Zn, and an ion source layer 3 containing any element of Te, S, Se is formed, and a memory thin film (memory layer) 4 having a relatively high resistance value is formed thereon. An upper electrode 6 is formed and connected to the memory thin film 4 through an opening formed in the insulating layer 5 on the memory thin film 4.

For the lower electrode 2, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, WN, TaN, silicide, or the like can be used.
When a TiW film, for example, is used for the lower electrode 2, the film thickness may be in the range of 10 nm to 100 nm, for example.

  The ion source layer 3 includes at least one of Cu, Ag, Zn, and at least one of Te, Se, S chalcogenide elements, CuTe, GeSbTe, CuGeTe, AgGeTe, AgTe, ZnTe, ZnGeTe. , CuS, CuGeS, CuSe, CuGeSe, etc., and boron or a rare earth element and silicon can be used to form the ion source layer 3.

In particular, the portion where the resistance value changes is limited to the memory thin film (memory layer) 4 having a relatively high resistance value, and a material having a sufficiently low resistance compared to the high resistance memory thin film 4 (for example, It is desirable to use Te as the chalcogenide element of the ion source layer 3 from the viewpoint of being lower than the resistance value when the memory thin film 4 is turned on, and Cu, Ag, It is desirable to form the ion source layer 3 from a material containing Zn, which contains CuTe, AgTe, and ZnTe as a main component.
Furthermore, when Cu is used as an element that becomes a cation of the ion source layer 3 and CuTe is included, the resistance of the ion source layer 3 is lowered and the resistance change of the ion source layer 3 is reduced. 4 is more preferable because it can be made sufficiently smaller than the resistance change of 4, and the stability of the memory operation can be improved.
For example, when a CuGeTe film is used for the ion source layer 3, the film thickness may be set to 5 nm to 50 nm, for example.

The insulating layer 5 includes, for example, a hard-cured photoresist, SiO 2 or Si 3 N 4 generally used for semiconductor devices, and other materials such as SiON, SiOF, Al 2 O 3 , Ta 2 O 5 , Inorganic materials such as HfO 2 and ZrO 2 , fluorine organic materials, aromatic organic materials, and the like can be used.
As with the lower electrode 2, a normal semiconductor wiring material is used for the upper electrode 6.

In the memory element 10 of this embodiment, in particular, the memory thin film (memory layer) 4 is made of any one of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixture thereof. It is composed of materials.
Since these oxides have a high melting point, the microstructure of the memory thin film 4 can be stabilized against a temperature rise.
Thereby, since the heat resistance of the memory thin film (memory layer) 4 can be improved, the manufacturing yield of the memory element 10 under a high temperature process can be improved.
In addition, stability against a local temperature rise during the operation of the storage element 10 such as recording / erasing can be improved, and for example, the number of rewrites can be increased.
Furthermore, the high resistance state can be stably maintained even during long-term data storage in a high temperature environment or the like.

Further, the memory thin film (memory layer) 4 made of the above-described oxide has a sufficient withstand voltage even when the film thickness is reduced.
Thus, a high resistance state can be easily realized and defects such as pinholes can be reduced, so that information can be recorded stably.

  The storage element 10 of this embodiment can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 3 containing Cu, Ag, and Zn, and a positive voltage is applied to the memory element 10 so that the upper electrode 6 side becomes negative. . As a result, Cu, Ag, Zn is ionized from the ion source layer 3 and diffuses in the memory thin film 4, and is combined with electrons on the upper electrode 6 side to be deposited, or in the memory thin film 4. Stays diffuse.
Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the memory thin film 4 or a large number of defects due to Cu, Ag, Zn are formed inside the memory thin film 4, so that the memory thin film The resistance value of 4 becomes low. Each layer other than the memory thin film 4 originally has a lower resistance value than the resistance value of the memory thin film 4 before recording. Therefore, by reducing the resistance value of the memory thin film 4, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc., but in the erasing process, for example, an ion source layer 3 containing Cu, Ag, Zn is formed on the ion source layer 3. A negative potential (−potential) is applied, and a negative voltage is applied to the memory element 10 so that the upper electrode 6 side becomes positive. As a result, Cu, Ag, and Zn constituting the current path or impurity level formed in the memory thin film 4 are ionized, move in the memory thin film 4, and return to the ion source layer 3 side.
Then, the current path or defect due to Cu, Ag, Zn disappears from the memory thin film 4, and the resistance value of the memory thin film 4 increases. Since each layer other than the memory thin film 4 originally has a low resistance value, the resistance value of the memory element 10 as a whole can be increased by increasing the resistance value of the memory thin film 4.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

In particular, the ion source layer 3 contains an element selected from Te, S, Se, that is, a chalcogen element in addition to the above-described metal elements (Cu, Ag, Zn), so that the metal element in the ion source layer 3 is obtained. (Cu, Ag, Zn) and a chalcogen element (Te, S, Se) are combined to form a metal chalcogenide layer. The metal chalcogenide layer mainly has an amorphous structure. For example, when a positive potential is applied to the side of the lower electrode 2 in contact with the ion source layer 3 made of the metal chalcogenide layer, the metal element contained in the metal chalcogenide layer (Cu, Ag, Zn) is ionized and diffused into the memory thin film 4 exhibiting high resistance, and is combined with the electrons and deposited on a part of the upper electrode 6 side, or in the memory thin film 4 By forming the impurity level of the insulating film, the resistance of the memory thin film 4 is lowered, and information can be recorded.
From this state, when a negative potential is applied to the lower electrode 2 side in contact with the ion source layer 3 made of a metal chalcogenide layer, the metal elements (Cu, Ag, Zn) deposited on the upper electrode 6 side are ionized again, By returning to the metal chalcogenide layer, the resistance of the memory thin film 4 returns to the original high state, and the resistance of the memory element 10 is also increased, so that the recorded information can be erased.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

The memory thin film 4 generally has a high resistance in the initial state before recording. However, the memory thin film 4 exhibits a low resistance in the initial recording state by plasma treatment, annealing treatment, or the like in the process step. It doesn't matter.
The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the memory thin film 4, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recorded data, it is sufficient that the ratio of the initial resistance value and the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance value after recording. Is 50 Ω, or the resistance value before recording is 100 kΩ and the resistance value after recording is 50 kΩ, and the initial resistance value of the memory thin film 4 is set to satisfy such a condition. . The resistance value of the memory thin film 4 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials.

  According to the configuration of the memory element 10 of the above-described embodiment, by adopting a configuration in which the ion source layer 3 and the memory thin film 4 are sandwiched between the lower electrode 2 and the upper electrode 6, for example, When a positive voltage (+ potential) is applied to the ion source layer 3 side so that the upper electrode 6 side becomes negative, a current path containing a large amount of Cu, Ag, and Zn is formed in the memory thin film 4. In addition, by forming a large number of defects due to Cu, Ag, and Zn in the memory thin film 4, the resistance value of the memory thin film 4 is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored by utilizing a change in the resistance value of the memory element 10, in particular, a change in the resistance value of the memory thin film 4, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

  Further, for example, when used in a storage device that can be erased in addition to recording such as RAM and EEPROM, for example, a negative voltage ( -Potential) is applied so that the upper electrode 6 side becomes positive. As a result, the current path or defect due to Cu, Ag, Zn formed in the memory thin film 4 disappears, the resistance value of the memory thin film 4 increases, and the resistance value of the entire memory element 10 increases. Become. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

Further, according to the memory element 10 of the present embodiment, the memory thin film (memory layer) 4 is made of any one of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or those By adopting a structure made of a mixed material, the melting point of these oxides is high, so that the microstructure of the memory layer 4 can be stabilized against a temperature rise.
As a result, the heat resistance of the memory thin film (memory layer) 4 can be improved, so that the manufacturing yield of the memory element 10 under a high-temperature process can be improved, and the operation of the memory element 10 such as recording / erasing can be improved. Improves stability against local temperature rise at the time, for example, can increase the number of times of repeated rewrites, and maintain a high resistance state stably even when storing long-term data under high temperature environment etc. be able to.
In addition, the memory thin film (memory layer) 4 made of the above-mentioned oxide has a sufficient withstand voltage even if the film thickness is reduced, so that a high resistance state can be easily realized and a pinhole or the like can be realized. Since defects can be reduced, information can be recorded stably.

Further, according to the memory element 10 of the present embodiment, the lower electrode 2, the ion source layer 3, the memory thin film 4, and the upper electrode 6 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

In the memory element 10 of the above-described embodiment, the oxide thin film of the memory thin film 4 is formed by a method using an oxide sputtering target or an inert gas such as argon as an introduced gas during sputtering using a metal target. It can be formed by using a method of introducing oxygen together with a gas, a method such as so-called reactive sputtering.
Furthermore, in addition to sputtering, an oxide thin film can be formed by a method such as CVD or vapor deposition. In addition, the film is in a metal state at the time of film formation, and thereafter a method such as thermal oxidation or chemical treatment. It is also possible to form an oxide thin film.

The memory element 10 of FIG. 1 can be manufactured as follows, for example.
First, a lower electrode 2, for example, a Ta film is deposited on a substrate 1 having high electrical conductivity, for example, a silicon substrate doped with a high concentration of P-type impurities.

  Next, an ion source layer 3 such as a CuTeGe film is formed, and then a memory thin film 4 such as a tantalum oxide film is formed.

  Thereafter, the insulating layer 5 is formed so as to cover the memory thin film 4, but a part of the insulating layer 5 is removed by photolithography to form a contact portion to the memory thin film 4.

Subsequently, for example, a W film is formed as the upper electrode 6 by, for example, a magnetron sputtering apparatus.
Thereafter, the W film is patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
In this way, the memory element 10 shown in FIG. 1 can be manufactured.

By using the memory element 10 of the above-described embodiment and arranging a large number of memory elements 10 in, for example, a column shape or a matrix shape, a memory device (memory) can be configured.
For each memory element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 6 side are provided. For example, each memory element 10 is arranged near the intersection of these wirings. What should I do?

  Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the upper electrode 6 is formed in common in the memory cell in the column direction, and a current is applied by applying a potential. By selecting the lower electrode 2 and the wiring to be flown, a memory cell to be recorded is selected, and a current is passed through the memory element 10 of this memory cell to record information or erase the recorded information. it can.

The storage element 10 according to the above-described embodiment can easily and stably record information and read information, and has particularly excellent characteristics in high temperature environment and long-term data retention stability. .
Further, even when the memory element 10 according to the above-described embodiment is miniaturized, it becomes easy to record information and hold the recorded information.
Therefore, by configuring the storage device using the storage element 10 of the above-described embodiment, the storage device can be integrated (high density) or downsized.

(Example)
Next, the memory element 10 of the above-described embodiment was actually manufactured and the characteristics were examined.

<Experiment 1>
On the silicon wafer, a Ta film is deposited as a lower electrode 2 with a thickness of 20 nm, and a Cu 50 Te 35 Ge 15 film is formed as a ion source layer 3 with a thickness of 20 nm on the silicon wafer. A tantalum film was formed, a photoresist was formed so as to cover the surface, and then exposure and development were performed by a photolithography technique to form an opening (through hole) in the photoresist on the memory thin film 4. Among these, the tantalum oxide film was formed by forming a metallic tantalum film with a thickness of 1 nm by sputtering and then performing an oxidation treatment in an oxygen-containing plasma atmosphere. The tantalum oxide film is presumed to be slightly thicker than the original tantalum film due to this oxidation treatment.
Thereafter, annealing was performed in vacuum to alter the photoresist, and the insulating layer 5 was formed as a hard cure resist that was stable with respect to temperature, etching, and the like. The hard-cure resist is used for the insulating layer 5 because it can be easily formed experimentally. In the case of manufacturing a product, another material (for example, a silicon oxide film) is used for the insulating layer 5. Better.
Next, a Ta film having a thickness of 100 nm was formed as the upper electrode 6. Thereafter, the upper electrode 6 deposited on the insulating layer 5 made of a hard-cure resist was patterned by a photolithography technique using a plasma etching apparatus.
A memory element 10 having such a structure was manufactured and used as a sample 1.

A memory element 10 was produced in the same manner as Sample 1 except that the thickness of the tantalum film serving as the tantalum oxide film of the memory thin film 4 was set to 3 nm.
Further, a memory element 10 was produced in the same manner as Sample 1 except that the thickness of the tantalum film serving as the tantalum oxide film of the memory thin film 4 was set to 5 nm.
In the sample 3 in which the thickness of the tantalum film is 5 nm, the oxidation treatment does not reach all the tantalum films, and the memory thin film 4 is a tantalum oxide film partially deficient in oxygen.

The IV characteristics were measured for the samples 1 to 3 respectively.
The IV measurement was performed as follows.
For the memory element of each sample, the back surface of the low-resistance silicon substrate 1 electrically connected to the lower electrode 2 was connected to the ground potential (ground potential), and a negative potential (−potential) was applied to the upper electrode 6.
Then, the negative potential applied to the upper electrode 6 was decreased from 0 V, and the change in current was measured. However, the current limiter is set to operate when the current reaches 1 mA, and beyond that, the negative potential applied to the upper electrode 6, that is, the absolute value of the voltage applied to the memory element is not increased. did.
Further, from the state where the current reached 1 mA and the current limiter was operated, the negative potential applied to the upper electrode 6 was decreased to 0 V, and the change in current was measured. Subsequently, this time, a positive potential was applied to the upper electrode 6, and the operation of returning the potential to 0 potential again was performed after increasing the application of the positive voltage to such a voltage that the current decreased and no current flowed.
The measurement results of the IV characteristics obtained in this way are shown in FIGS. 2A to 2C. 2A shows the measurement result of sample 1, FIG. 2B shows the measurement result of sample 2, and FIG. 2C shows the result of sample 3.

  2A to 2C, it can be seen that in any sample, repeated recording and erasing operations are stably performed even with a recording current of 1 mA and a considerably large current.

<Experiment 2>
Instead of the memory element 10 shown in FIG. 1, as another embodiment of the present invention, the memory element 20 shown in FIG. 3 was fabricated and the characteristics were examined.
The memory element 20 shown in FIG. 3 has a memory thin film (memory layer) 4 as a lower layer than the ion source layer 3, contrary to the memory element 10 of the previous embodiment shown in FIG. The upper electrode 6 is formed in the same pattern as the memory thin film 4 and the ion source layer 3. The lower electrode 2 is formed in a smaller pattern and is embedded in the opening formed in the insulating film 5.

  In the memory element 20 shown in FIG. 3 as well, the memory thin film (memory layer) 4 is formed by configuring the memory thin film (memory layer) 4 with the above-described oxide film, similarly to the memory element 10 of the previous embodiment. To improve the manufacturing yield of the memory element 20 under a high-temperature process, to improve the stability against a local temperature rise during the operation of the memory element 20, and to increase the number of rewrites possible In addition, it is possible to stably maintain a high resistance state when storing long-term data in a high temperature environment.

The memory element 20 having such a configuration can be manufactured as follows.
An insulating film (for example, Al 2 O 3 , Ta 2 O 5, etc.) 5 is uniformly deposited on the silicon substrate 1 having a low resistivity by sputtering, and then a lower electrode formation pattern (pattern portion is formed by photolithography). (Without resist) is formed of a photoresist, and then the insulating film 5 is partially removed by RIE (Reactive Ion Etching).
Next, a material (for example, W) for forming the lower electrode 2 is uniformly deposited by sputtering. Thereafter, the surface is processed by CMP (Chemical Mechanical Polishing) to flatten the surface so that the lower electrode material remains only in the lower electrode formation pattern. Thereby, the lower electrode 2 is formed in a predetermined pattern.
Next, each layer of the memory thin film (memory layer) 4, the ion source layer 3, and the upper electrode 6 is continuously formed by sputtering.
Thereafter, these films 4, 3, and 6 are patterned by photolithography and etching, whereby the memory element 20 having the structure of FIG. 3 can be manufactured.

  In the structure of the memory element 20 shown in FIG. 3 and the structure of the memory element 10 shown in FIG. 1, the vertical positional relationship between the ion source layer 3 and the memory thin film 4 is opposite and the film formation order is different. Therefore, especially in the thin memory film 4 having a small film thickness, the memory characteristics differ depending on the state of the underlying film. In the memory element 10 shown in FIG. 1, the base film immediately below the memory thin film 4 is the ion source layer 3, whereas in the memory element 20 shown in FIG. 3, the base film immediately below the memory thin film 4 is the lower electrode 2. And the insulating film 5.

Then, by the manufacturing method described above, a W film is deposited as a lower electrode 2 to a thickness of 200 nm on a silicon wafer, and a hafnium oxide film as a memory thin film 4 is formed thereon to a thickness of 2 nm. A Cu 50 Te 31 Ge 13 Hf 6 film having a thickness of 20 nm is formed as the layer 3, and a W film is formed as the upper electrode 5 having a thickness of 200 nm to produce the memory element 20 shown in FIG. Four samples were obtained. The insulating film 5 was a silicon oxide film, and the size of the lower electrode formation pattern was about 1 μmφ.
In addition, the memory element 20 was manufactured in the same manner as the sample 4 except that the thickness of the hafnium oxide film of the memory thin film 4 was set to 4 nm.

A tantalum oxide film is formed as the insulating film 5, a niobium oxide film is formed as the memory thin film 4 with a thickness of 2 nm, a Cu 50 Te 31 Ge 13 Gd 6 film is formed as the ion source layer 3, and the others are samples. The memory element 20 was produced in the same manner as in Example 4, and the sample 6 was obtained.
Further, the memory element 20 was produced in the same manner as the sample 6 except that the thickness of the niobium oxide film of the memory thin film 4 was set to 4 nm.

A zirconium oxide film having a thickness of 2.4 nm is formed as the memory thin film 4, a Cu 50 Te 31 Ge 13 Zr 6 film is formed as the ion source layer 3, and the memory element 20 is formed in the same manner as in the sample 6 except for the above. The sample 8 was prepared.
In addition, the memory element 20 was produced in the same manner as the sample 8 except that the thickness of the zirconium oxide film of the memory thin film 4 was set to 4.8 nm.

An aluminum oxide film having a thickness of 1.2 nm is formed as the memory thin film 4, a Cu 52 Te 33 Ge 15 film is formed as the ion source layer 3, and the memory element 20 is fabricated in the same manner as the sample 6 except for the above. Sample 10 was obtained.
Further, the memory element 20 was produced in the same manner as the sample 10 except that the film thickness of the aluminum oxide film of the memory thin film 4 was set to 2.4 nm.
In addition, the memory element 20 was produced in the same manner as the sample 10 except that the film thickness of the aluminum oxide film of the memory thin film 4 was 3.6 nm.

In these samples 4 to 12, since the surface state of the lower electrode 2 is controlled particularly by the CMP method, the lower electrode is observed with any sample when observed with an AFM (atomic force microscope). It was found that the surface roughness Ra of the surface 2 can be reduced to 0.8 nm or less.
Thus, it can be seen that since the surface roughness Ra of the lower electrode 2 can be reduced, good memory characteristics can be obtained.

  Further, the IV characteristics were measured for the storage elements 20 of the samples 4 to 12 respectively. The measurement results of the IV characteristics are shown in FIGS. 4A to 7C. 4A shows the measurement result of sample 4, and FIG. 4B shows the measurement result of sample 5. FIG. 5A shows the measurement result of Sample 6, and FIG. 5B shows the measurement result of Sample 7. 6A shows the measurement result of Sample 8, and FIG. 6B shows the measurement result of Sample 9. FIG. 7A shows the measurement result of the sample 10, FIG. 7B shows the measurement result of the sample 11, and FIG. 7C shows the measurement result of the sample 12.

  In any sample, it can be seen that repeated memory operation is stably performed even with a large current of 1 mA.

The melting points of various oxide films used for the memory thin films 4 of Samples 1 to 12 are as high as tantalum oxide 1880 ° C., hafnium oxide 2770 ° C., niobium oxide 1900 ° C., zirconium oxide 2680 ° C., and aluminum oxide 2050 ° C. Yes. That is, since any material is excellent in heat resistance, a stable memory operation can be obtained even when a large current flows locally.
Therefore, by using these oxide films having a high melting point for the memory thin film (memory layer) 4, it is possible to realize a memory element having excellent heat stability (for example, repeated rewriting durability).

<Experiment 3>
(Repetitive recording / erasing test)
Next, with respect to the sample of the memory element 20 similar to that used in Experiment 2, a measurement apparatus was configured as shown in FIG. 8 and repeated recording / erasing tests were performed.
The measuring apparatus shown in FIG. 8 includes an arbitrary waveform generator 31 and a digital oscilloscope 32.
The arbitrary waveform generator 31 is connected via a pulse application line 33 to a load resistor surrounded by a broken line. Further, the digital oscilloscope 32 is connected to a load resistor via two voltage monitor lines 34. The load resistance has two resistance lines having a resistance value of 50Ω and a resistance value R L (2 kΩ).
Then, connection wirings are connected to the substrate (back side) of the wafer 35 and the upper electrode side from the load resistance, respectively.

Using the measuring apparatus having this configuration, a recording pulse (about 1 V) having a pulse width of 1 ms is applied from the arbitrary waveform generator 31 through the pulse applying line 33 to record information in the storage element 20 in the wafer 35, and then 1 ms. The recording process to read out was performed. Further, similarly, an erase pulse (about 1 V) of 1 ms is applied from the arbitrary waveform generator 31 through the pulse application line 33 to erase the information recorded in the memory element 20 in the wafer 35, and thereafter an erase process of reading out in 1 ms is performed. It was. Then, the recording process and the erasing process were continuously repeated, and the state change was observed with the digital oscilloscope 32. From the state obtained with the digital oscilloscope 32, the resistance value of the memory element 20 was obtained.
As a result of repeated recording and erasing, the resistance value after the erasing process (high resistance state) gradually decreases, and both processes are performed until the resistance value after the recording process (low resistance state) is reduced to twice. The number of repetitions was defined as the number of repetitions.
The sample used was a sample 5 sample using hafnium oxide for the memory thin film 4, a sample 7 sample using niobium oxide for the memory thin film 4, a sample 9 sample using zirconium oxide for the memory thin film 4, There are four types of samples 12 using aluminum oxide for the memory thin film 4.
For each sample, the same measurement was repeated three times.
The measured values of the number of repetitions are shown in Table 1 together with the film thickness, melting point, and atomic radius of the metal element constituting the oxide of the oxide film of the memory thin film 4. The atomic radius of each metal element is as follows: hafnium oxide hafnium Hf is 0.155 nm, niobium oxide niobium Nb is 0.145 nm, zirconium oxide zirconium Zr is 0.155 nm, and aluminum oxide aluminum Al is 0.125 nm. Yes.

From Table 1, niobium oxide and aluminum oxide was seen deterioration in repeated tests, deterioration in repetition of 106 times in the hafnium oxide zirconium oxide (million times) was observed.
The reason why the resistance value after the erasing process gradually decreases is that the Joule heat due to the current at the time of repeated recording / erasing and the ion source element (Cu element in this sample) are repeatedly moved and damaged, This is probably because the insulating property of the oxide film of the memory thin film 4 is lowered.
A high melting point of the oxide film is effective for deterioration due to Joule heat, and a large atomic size is effective for movement of the ion source element.
From Table 1, it can be seen that hafnium oxide and zirconium oxide, which actually have a high melting point and a large atomic radius, have a large number of repetitions.

Therefore, for example, it is considered that the number of repetitions can be increased by setting the melting point of the oxide constituting the memory thin film (memory layer) to preferably 1800 ° C. or higher, more preferably 2100 ° C. or higher.
In addition, it is considered that the number of repetitions can be increased by setting the atomic radius of the metal element constituting the oxide thin film of the memory thin film (memory layer) to more preferably 0.15 nm or more.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of the memory element of one embodiment of this invention. A is a measurement result of IV characteristics of the memory element of Sample 1. B is a measurement result of IV characteristics of the memory element of Sample 2. C is a measurement result of IV characteristics of the memory element of Sample 3. It is a schematic block diagram (sectional drawing) of the memory element of other embodiment of this invention. A is a measurement result of IV characteristics of the memory element of Sample 4. B is a measurement result of IV characteristics of the memory element of Sample 5. A is a measurement result of IV characteristics of the memory element of Sample 6. B is a measurement result of IV characteristics of the memory element of Sample 7. A is a measurement result of IV characteristics of the memory element of Sample 8. B is a measurement result of IV characteristics of the memory element of Sample 9. A is a measurement result of IV characteristics of the memory element of sample 10. B is a measurement result of IV characteristics of the memory element of Sample 11. C is a measurement result of IV characteristics of the memory element of sample 12. It is a figure which shows schematic structure of the measuring apparatus of a repeated recording / erasing test.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower electrode, 3 Ion source layer, 4 Memory thin film (memory layer), 5 Insulating layer (insulating film), 6 Upper electrode, 10, 20 Memory element

Claims (4)

  1. A storage layer and an ion source layer are sandwiched between the first electrode and the second electrode ,
    The ion source layer comprises CuTe;
    The memory element, wherein the memory layer is made of any one of tantalum oxide, niobium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a mixed material thereof.
  2.   The memory element according to claim 1, wherein the memory layer is made of aluminum oxide.
  3. A storage layer and an ion source layer are sandwiched between the first electrode and the second electrode, the ion source layer includes CuTe, and the storage layer includes tantalum oxide and niobium oxide. A storage element made of any of aluminum oxide, hafnium oxide, zirconium oxide, or a mixture thereof;
    Wiring connected to the first electrode side;
    A wiring connected to the second electrode side,
    A storage device in which a large number of the storage elements are arranged.
  4.   The storage device according to claim 3, wherein the storage layer is made of aluminum oxide.
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Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5135796B2 (en) * 2004-12-28 2013-02-06 日本電気株式会社 Switching element and rewritable logic integrated circuit
US8203133B2 (en) 2004-12-28 2012-06-19 Nec Corporation Switching element, reconfigurable logic integrated circuit and memory element
JP2006319028A (en) * 2005-05-11 2006-11-24 Nec Corp Switching element, rewritable logic integrated circuit, and memory element
JP4396621B2 (en) * 2005-12-02 2010-01-13 ソニー株式会社 Storage element and storage device
KR100684908B1 (en) * 2006-01-09 2007-02-13 삼성전자주식회사 Multi-resistive state memory element, memory cell, operating thereof, and data processing system using the memory element
JP4983102B2 (en) * 2006-06-06 2012-07-25 Tdk株式会社 Dielectric element
KR101159075B1 (en) * 2006-06-27 2012-06-25 삼성전자주식회사 Variable resistance random access memory device comprising n+ interfacial layer
US7772581B2 (en) * 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
WO2008038365A1 (en) * 2006-09-28 2008-04-03 Fujitsu Limited Variable-resistance element
US8766224B2 (en) 2006-10-03 2014-07-01 Hewlett-Packard Development Company, L.P. Electrically actuated switch
JP5010891B2 (en) 2006-10-16 2012-08-29 国立大学法人 名古屋工業大学 Variable resistance element
JP5092355B2 (en) * 2006-10-31 2012-12-05 ソニー株式会社 Storage device
JP2008153375A (en) * 2006-12-15 2008-07-03 Sony Corp Storage element and device
JP5627166B2 (en) 2007-05-09 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Manufacturing method of semiconductor memory device
US8022502B2 (en) * 2007-06-05 2011-09-20 Panasonic Corporation Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element
JP5227544B2 (en) 2007-07-12 2013-07-03 株式会社日立製作所 Semiconductor device
CN101755338B (en) * 2007-07-18 2012-10-10 松下电器产业株式会社 Current limiting element, memory device using current limiting element
JP4539885B2 (en) * 2007-08-06 2010-09-08 ソニー株式会社 Storage element and storage device
JP2009043905A (en) * 2007-08-08 2009-02-26 Hitachi Ltd Semiconductor device
JP5194640B2 (en) * 2007-08-22 2013-05-08 ソニー株式会社 Storage element and storage device
US8338816B2 (en) * 2007-10-15 2012-12-25 Panasonic Corporation Nonvolatile memory element, and nonvolatile semiconductor device using the nonvolatile memory element
JP2010287582A (en) * 2007-10-15 2010-12-24 Panasonic Corp Nonvolatile storage element and method of manufacturing the same, and nonvolatile semiconductor device using the nonvolatile storage element
JP4466738B2 (en) * 2008-01-09 2010-05-26 ソニー株式会社 Storage element and storage device
WO2009141857A1 (en) * 2008-05-22 2009-11-26 パナソニック株式会社 Resistance change nonvolatile memory device
WO2009157479A1 (en) * 2008-06-26 2009-12-30 日本電気株式会社 Switching element and switching element manufacturing method
WO2010074689A1 (en) 2008-12-23 2010-07-01 Hewlett-Packard Development Company, L.P. Memristive device and methods of making and using the same
WO2010082922A1 (en) 2009-01-13 2010-07-22 Hewlett-Packard Development Company, L.P. Memristor having a triangular shaped electrode
JP2010177393A (en) * 2009-01-29 2010-08-12 Sony Corp Semiconductor storage device and method of manufacturing the same
US8278657B2 (en) * 2009-02-13 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Transistor, semiconductor device including the transistor, and manufacturing method of the transistor and the semiconductor device
JP2010251529A (en) 2009-04-16 2010-11-04 Sony Corp Semiconductor memory device and method of manufacturing the same
US8363463B2 (en) 2009-06-25 2013-01-29 Macronix International Co., Ltd. Phase change memory having one or more non-constant doping profiles
JP5471134B2 (en) 2009-08-05 2014-04-16 ソニー株式会社 Semiconductor memory device and manufacturing method thereof
JP2011124511A (en) * 2009-12-14 2011-06-23 Sony Corp Storage element and storage device
JP2011211101A (en) 2010-03-30 2011-10-20 Sony Corp Memory device and method of manufacturing the same
JP2012019042A (en) * 2010-07-07 2012-01-26 Sony Corp Memory element and memory device
JP2012060024A (en) * 2010-09-10 2012-03-22 Sony Corp Storage element and storage device
US9000506B2 (en) 2010-11-19 2015-04-07 Panasonic Intellectual Property Management Co., Ltd. Variable resistance nonvolatile memory element and method for manufacturing the same
JP5728919B2 (en) * 2010-12-09 2015-06-03 ソニー株式会社 Storage element and storage device
US8426242B2 (en) 2011-02-01 2013-04-23 Macronix International Co., Ltd. Composite target sputtering for forming doped phase change materials
JP5807789B2 (en) * 2011-02-02 2015-11-10 日本電気株式会社 Switching element, semiconductor device and manufacturing method thereof
CN102694118A (en) * 2011-03-22 2012-09-26 中国科学院微电子研究所 A resistance random access memory and a preparation method thereof
JP5724651B2 (en) * 2011-06-10 2015-05-27 ソニー株式会社 Storage element and storage device
US8946666B2 (en) 2011-06-23 2015-02-03 Macronix International Co., Ltd. Ge-Rich GST-212 phase change memory materials
JP2013016530A (en) 2011-06-30 2013-01-24 Sony Corp Memory element, method for manufacturing the same, and memory device
WO2013035695A1 (en) * 2011-09-08 2013-03-14 Jx日鉱日石金属株式会社 Cu-te-alloy-based sintered body sputtering target
US8932901B2 (en) 2011-10-31 2015-01-13 Macronix International Co., Ltd. Stressed phase change materials
US9099633B2 (en) 2012-03-26 2015-08-04 Adesto Technologies Corporation Solid electrolyte memory elements with electrode interface for improved performance
US9847480B2 (en) * 2012-09-28 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Resistance variable memory structure and method of forming the same
JP5672329B2 (en) * 2013-04-08 2015-02-18 日本電気株式会社 Switching element
TWI549229B (en) 2014-01-24 2016-09-11 旺宏電子股份有限公司 Multiple phase change materials in a memory device for system on a chip application
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching
CN107694588A (en) * 2016-08-08 2018-02-16 松下电器产业株式会社 Manufacture method, photosemiconductor and the device for producing hydrogen of photosemiconductor
CN107104184A (en) * 2017-06-23 2017-08-29 河南工程学院 Flexible resistance-variable storing device of a kind of sol-gel films and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003233406A1 (en) * 2002-03-15 2003-09-29 Axon Technologies Corporation Programmable structure, an array including the structure, and methods of forming the same
JP4613478B2 (en) * 2003-05-15 2011-01-19 ソニー株式会社 Semiconductor memory element and semiconductor memory device using the same
US7129133B1 (en) * 2004-09-13 2006-10-31 Spansion Llc Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film

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