JP2007189086A - Storage element, manufacturing method thereof and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage element capable of suppressing variations in the characteristics, such as threshold voltages in recording, reading and writing of information, and having appropriate characteristics. <P>SOLUTION: The storage element 10 is configured, such that a storage layer 5 is sandwiched between a first electrode 1 and a second electrode 4, the storage layer 5 comprises an oxide layer 2 and an ionized layer 3 containing Cu which are laminated, the oxide layer 2 consists of a rare earth element oxide, and the ionized layer 3 contains one or more kinds of elements selected from among S, Se and Te. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory element capable of recording information, a manufacturing method thereof, and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, flash memories, FeRAMs (ferroelectric memories), MRAMs (magnetic storage elements), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.
Accordingly, extensive research and product development have been conducted on the various types of nonvolatile memories described above.

However, the various nonvolatile memories described above have advantages and disadvantages.
Flash memory has a high degree of integration, but is disadvantageous in terms of operation speed.
FeRAM is limited in microfabrication for high integration and has a problem in the manufacturing process.
MRAM has a problem of power consumption.

Therefore, a new type of storage element has been proposed that is particularly advantageous for the limit of microfabrication of the memory element.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. By diffusing, electrical characteristics such as resistance value or capacitance of the ionic conductor change.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, more specifically, a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Ag, Cu, and Zn (see Patent Document 1).

Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104)

  In the configuration of the memory element described above, the threshold voltage when the resistance value of the memory element transitions and the variation of the threshold voltage, the initial resistance value of the memory element, the resistance value such as the resistance value of the high resistance state after the transition, and the Variations have a significant effect on memory operating characteristics.

In the structure of the memory element described above, for example, when manufacturing a large-capacity memory having a large-scale cell array, so-called “writing” that transitions from a high-resistance state to a low-resistance state to prevent erroneous recording. It is necessary to suppress the threshold voltage of the operation, or conversely, the threshold voltage of the so-called “erase” operation for transitioning from the low resistance state to the high resistance state to a voltage within a constant and sufficiently low range. If it is out of a certain range, writing and erasing errors are caused.
These threshold values vary depending on repeated writing and erasing even in the same memory element, or the threshold voltage changes with each repetition, or the threshold voltage for writing is different for each memory element (that is, for each memory cell of the memory). If there are variations in threshold values, such as different values, stable memory operation becomes difficult.
In addition, when the threshold voltage is too high, high-speed operation becomes difficult, or the voltage drive range of the selection MOS transistor for selecting the memory cell is exceeded, and the operation becomes impossible. Exists.

  In addition, when a memory element receives heat due to a thermal history or the like in the manufacturing process, the operating characteristics generally change, so that the threshold voltage increases and high-speed operation becomes difficult, and information retention characteristics Deteriorated and the resistance state is likely to change.

  In order to solve the above-described problem, in the present invention, variation in characteristics such as threshold voltage in recording, reading, and writing of information can be suppressed, and a memory element having appropriate characteristics, a manufacturing method thereof, and memory A memory device using the element is provided.

  The memory element of the present invention is configured by sandwiching a memory layer between a first electrode and a second electrode, and the memory layer includes an oxide layer, an ionized layer containing Cu to be ionized, and The oxide layer is made of a rare earth element oxide, and the ionized layer contains one or more elements selected from S, Se, and Te.

  The method for manufacturing a memory element according to the present invention provides an oxide layer made of copper oxide when manufacturing a memory element in which a memory layer is sandwiched between a first electrode and a second electrode. And a step of forming an ionized layer containing a rare earth element, and one or more elements selected from Cu, S, Se, and Te, to form a laminated film in which an oxide layer and an ionized layer are laminated. Then, by a heat treatment step, Cu is diffused from the oxide layer to the ionized layer, and a rare earth element is diffused from the ionized layer to the oxide layer, thereby forming a rare earth element oxide in the oxide layer and oxidizing. A memory layer composed of a physical layer and an ionized layer is produced.

  A memory device of the present invention includes the memory element of the present invention, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. Is.

  According to the configuration of the memory element of the present invention described above, the memory layer is sandwiched between the first electrode and the second electrode, and this memory layer includes the oxide layer and the ionized Cu. By laminating the ionized layer containing, it is possible to store information by utilizing the change in the resistance state of the oxide layer included in the memory layer.

Specifically, for example, when a positive potential is applied to one electrode on the ionization layer side containing Cu and a positive voltage is applied to the memory element, Cu contained in the ionization layer is ionized to form an oxide layer. The resistance value of the oxide layer is lowered by diffusing to the other electrode and depositing by combining with the electrons on the other electrode side, or by forming an impurity level of the insulating film that remains in the oxide layer. Since the resistance value of the memory layer including the oxide layer becomes low, information can be written.
Also, from this state, when a negative potential is applied to one electrode on the ionization layer side and a negative voltage is applied to the memory element, Cu deposited on the other electrode side is ionized again, and is applied to one electrode side. By returning, the resistance value of the storage layer returns to the original high state, and the resistance value of the storage element also increases, so that the recorded information can be erased.

And since the memory layer has an oxide layer made of a rare earth element oxide, the resistance value in the high resistance state can be made relatively high. In addition, since the oxide layer made of a rare earth element oxide is thermally stable, information can be recorded stably with a very small current.
Further, the ionization layer contains one or more elements (chalcogenide elements) selected from S, Se, and Te, thereby promoting the ionization of Cu.

According to the method for manufacturing a memory element of the present invention described above, the step of forming an oxide layer made of copper oxide, and one or more elements selected from rare earth elements, Cu, S, Se, and Te (chalcogenide elements) And forming a layered film in which the oxide layer and the ionized layer are stacked, and then, by a heat treatment step, Cu is diffused from the oxide layer to the ionized layer, and from the ionized layer. Since the rare earth element is diffused into the oxide layer to form a memory layer by forming a rare earth element oxide in the oxide layer, the rare earth element has a necessary thickness and is thermally stable due to the diffusion of the rare earth element. An oxide layer can be formed.
Then, by controlling the content of the rare earth element in the ionized layer, the thickness of the oxide layer made of the rare earth element oxide can be easily controlled, so that the memory element has desirable operating characteristics. Can be controlled.

  Therefore, according to the method for manufacturing a memory element of the present invention, it is possible to reduce non-uniformity of the oxide layer and suppress variation in threshold voltage in writing and erasing of the memory element. In addition, it is possible to manufacture a memory element having excellent repetition characteristics of the erase operation.

  In addition, the threshold voltage in writing and erasing of the memory element can be kept low, writing and erasing can be performed in a short time, and a memory element that operates at high speed can be manufactured. This is considered because the ratio of the chalcogenide element and Cu in the ionized layer is optimized by the heat treatment.

According to the memory element and the memory device of the present invention described above, since the oxide layer is thermally stable, it is possible to suppress changes in operating characteristics when receiving heat during manufacturing.
Accordingly, variation in threshold voltage in writing and erasing to the storage element can be suppressed and an appropriate threshold voltage can be obtained, so that a storage element and a storage device having appropriate characteristics can be configured.

  Further, according to the manufacturing method of the present invention described above, it is possible to suppress variation in threshold voltage in writing and erasing to the memory element, so that the memory element and the memory device having appropriate characteristics can be stably provided. It can be manufactured with good yield.

In addition, since it becomes possible to reduce variations in threshold voltage, it is possible to reduce the occurrence of errors in writing and erasing information, so that a storage device capable of stable memory operation can be realized. It becomes possible.
In addition, since a memory element having excellent repetitive characteristics of writing and erasing operations can be manufactured, a memory device having excellent information retention durability and high reliability can be realized.

Furthermore, the memory element of the present invention can be manufactured by materials and manufacturing methods used in a normal MOS logic circuit manufacturing process.
Therefore, according to the present invention, a memory element and a memory device having appropriate characteristics can be manufactured at a low cost, and an inexpensive memory device can be provided.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element 10 is shown in FIG.
In the memory element 10, for example, a lower electrode 1, which is a connection portion with a CMOS circuit portion, is formed on a silicon substrate (see FIG. 2) on which a CMOS circuit is formed, and a memory layer is formed on the lower electrode 1. 5 is formed, and the upper electrode 4 is formed on the memory layer 5.

  The memory layer 5 is composed of a stack of an oxide layer 2 and an ionized layer 3 containing copper Cu that becomes ions.

For the lower electrode 1, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.
In addition, when using an electrode material that may cause ion conduction in an electric field such as Cu, it is used by covering the Cu electrode with a material that is difficult to ionize or thermally diffuse such as W, WN, TiN, or TaN. Also good.

The oxide layer 2 constituting the memory layer 5 is made of a rare earth element oxide.
The oxide layer 2 may be composed of only the rare earth element oxide, or the oxide layer 2 may be composed of Cu or other elements in addition to the rare earth element oxide.

  Moreover, the ionization layer 3 which comprises the memory layer 5 is set as the structure containing the element (chalcogenide element) chosen from Te, Se, S other than copper Cu.

For such an ionized layer 3, a material having a composition in which Cu is added to a compound of a chalcogenide element, for example, GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, or the like can be used.
In addition to the chalcogenide element and Cu, a rare earth element may be included in the ionized layer 3.
Furthermore, the ionization layer 3 may contain elements such as B, P, and N as additives.

  As with the lower electrode 1, a normal semiconductor wiring material is used for the upper electrode 4.

  The memory layer 5 (2, 3) configured as described above has a characteristic that the impedance of the oxide layer 2 changes when a voltage pulse or a current pulse is applied.

The memory element 10 of this embodiment can be operated as follows to store information.
First, for example, a positive potential (+ potential) is applied to the upper electrode 4, and a positive voltage is applied to the memory element 10 so that the lower electrode 1 side becomes negative. Thereby, Cu ions from the ionized layer 3 are ion-conducted in the oxide layer 2 and are combined with electrons on the lower electrode 1 side to be deposited, or remain in a state of being diffused inside the oxide layer 2.
Then, a current path containing a large amount of Cu is formed inside the oxide layer 2, so that the resistance value of the oxide layer 2 is lowered. Each layer other than the oxide layer 2 originally has a lower resistance value than the resistance value of the oxide layer 2 before recording. Therefore, by reducing the resistance value of the oxide layer 2, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc. In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 4, A negative voltage is applied to the memory element 10 so that the lower electrode 1 side is positive. As a result, Cu in the current path formed in the oxide layer 2 is ionized, and ion conduction is performed in the oxide layer 2 and dissolved in the ionized layer 3 or combined with Te to form a compound such as Cu ₂ Te. Form.

  Then, the current path due to Cu disappears or decreases from within the oxide layer 2 and the resistance value of the oxide layer 2 increases. Since each layer other than the oxide layer 2 originally has a relatively low resistance value, the resistance value of the entire memory element 10 can be increased by increasing the resistance value of the oxide layer 2.

  After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the memory element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  The material of the oxide layer 2 is preferably a material that exhibits a high resistance value in an initial state before recording and a state after erasing.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording, rather than the cell size of the memory element 10 and the material composition of the oxide layer 2, and the initial resistance value. Is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recording data, it is sufficient that the ratio of the initial resistance value to the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and the resistance after recording is It is sufficient if the value is 50Ω, or the resistance value before recording is 100 kΩ, and the resistance value after recording is 50 kΩ, and the initial resistance value of the oxide layer 2 is set to satisfy such a condition. The
The resistance value of the oxide layer 2 can be controlled by, for example, the amount of oxygen contained in the Cu oxide of the oxide layer 2 before the heat treatment, the amount of rare earth elements contained in the ionized layer 3, and the heat treatment temperature. Is possible.

  According to the configuration of the memory element 10 described above, the oxide layer 2 and the ionized layer 3 containing Cu are sandwiched between the lower electrode 1 and the upper electrode 4. 4, when a positive voltage (+ potential) is applied so that the lower electrode 1 side becomes negative, a current path containing a large amount of Cu is formed in the oxide layer 2, and the oxide layer 2 The resistance value is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is lowered is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored using a change in the resistance value of the memory element 10, particularly a change in the resistance value of the oxide layer 2, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

Further, for example, when used in a storage device that can be erased in addition to recording such as RAM and EEPROM, a negative voltage (−potential) is applied to the upper electrode 4 with respect to the storage element 10 in the state after recording described above. Is applied so that the lower electrode 1 side becomes positive.
Thereby, the current path due to Cu formed in the oxide layer 2 disappears, the resistance value of the oxide layer 2 becomes high, and the resistance value of the entire memory element 10 becomes high. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

Furthermore, according to the configuration of the memory element 10 described above, the oxide layer 2 of the memory layer 5 is made of a rare earth element oxide, so that the resistance value in the high resistance state can be made relatively high. In addition, since the oxide layer 2 made of rare earth element oxide is thermally stable, information can be stably recorded with a very small current.
In addition, since the ionization layer 3 of the memory layer 5 contains (chalcogenide element) in addition to Cu, ionization of Cu is promoted.

A memory device (memory device) can be configured by arranging a large number of memory elements 10 having the above-described configuration in a matrix.
For each memory element 10, a wiring connected to the lower electrode 1 side and a wiring connected to the upper electrode 4 side are provided. For example, each memory element 10 is disposed near the intersection of these wirings. What should I do?

Further, for example, it is conceivable to form a memory device by forming wirings connected to the upper electrode 4 in common for the entire memory cell array.
FIG. 2 and FIG. 3 show schematic configuration diagrams of an embodiment of the memory cell array configured as described above. 2 is a cross-sectional view, and FIG. 3 is a plan view.

  As shown in FIGS. 2 and 3, in this memory cell array, the memory element 10 constituting each memory cell shares the layers of the oxide layer 2, the ionized layer 3, and the upper electrode 4 over the entire memory cell. . In other words, each memory element 10 is composed of the same oxide layer 2, ionized layer 3, and upper electrode 4.

The upper electrode 4 formed in common is the plate electrode PL.
On the other hand, the lower electrode 1 is individually formed for each memory cell, and each memory cell is electrically isolated. A memory element 10 of each memory cell is defined at a position corresponding to each lower electrode 1 by the lower electrode 1 formed individually for each memory cell.
The lower electrode 1 is connected to a corresponding selection MOS transistor Tr.

As shown in FIG. 2, each storage element 10 constituting each memory cell of the memory cell array is formed above the MOS transistor Tr formed on the semiconductor substrate 11.
The MOS transistor Tr includes a source / drain region 13 formed in a region separated by the element isolation layer 12 in the semiconductor substrate 11 and a gate electrode 14. A sidewall insulating layer is formed on the wall surface of the gate electrode 14.
The gate electrode 14 also serves as a word line WL which is one address wiring of the memory element.
One of the source / drain regions 13 of the MOS transistor Tr and the lower electrode 1 of the memory element 10 are electrically connected via the plug layer 15, the metal wiring layer 16, and the plug layer 17.
The other of the source / drain regions 13 of the MOS transistor Tr is connected to the metal wiring layer 16 through the plug layer 15. This metal wiring layer 16 is connected to a bit line BL (see FIG. 3) which is the other address wiring of the memory element.

  In FIG. 3, the active region 18 of the MOS transistor Tr is indicated by a chain line. In FIG. 3, reference numeral 21 denotes a contact portion that communicates with the lower electrode 1 of the memory element 10, and 22 denotes a contact portion that communicates with the bit line BL.

The memory cell array shown in FIGS. 2 and 3 can be operated as follows, for example.
When the gate of the selection MOS transistor Tr is turned on by the word line WL and a voltage is applied to the bit line BL, the voltage is applied to the lower electrode 1 of the selected memory cell via the source / drain of the MOS transistor Tr. Is done.

Here, when the polarity of the voltage applied to the lower electrode 1 is a negative potential compared to the potential of the upper electrode 4 (plate electrode PL), the resistance value of the memory element 10 transitions to a low resistance state. To do. Thereby, information can be recorded in the memory element 10 of the selected memory cell.
Further, by applying a field voltage, which is a positive potential compared to the potential of the upper electrode 4 (plate electrode PL), to the lower electrode 1, the resistance value of the memory element 10 transitions to the high resistance state again. Thereby, the recorded information can be erased from the storage element 10 of the selected memory cell.

In order to read out recorded information, for example, a memory cell is selected by the MOS transistor Tr, a predetermined voltage or current is applied to the selected memory cell, and the resistance state of the memory element 10 is changed. Different currents or voltages are detected via a sense amplifier or the like connected to the tip of the bit line BL or the plate electrode PL.
At this time, the voltage or current applied to the selected memory cell is set to be smaller than the threshold voltage or current at which the resistance value of the memory element 10 changes.

By the way, in the ionization behavior excited by applying a voltage to the memory element 10 described above, or the change in resistance value due to the operation of ions, the threshold voltage and the writing and erasing speed when the resistance value changes are oxides. It depends greatly on the state of layer 2.
Generally, the shorter the time during which the write voltage is applied, the higher the write voltage is required. Similarly, in the erase operation, the shorter the time during which the erase voltage is applied, the greater the voltage required for erasure.
For this reason, in order to form the memory element 10 that can operate at a higher speed, the operation threshold voltage is kept low, and in order to perform a balanced operation for both recording and erasing, a rare earth oxide is used by an appropriate method and condition. It is necessary to form an oxide layer 2 made of

For example, when the rare earth element oxide is formed as the oxide layer 2 and the ionized layer 3 containing the rare earth element is formed thereon, the heat applied in the manufacturing process for forming the semiconductor or the subsequent heat treatment, When the rare earth element in the ionized layer 3 diffuses into the oxide layer 2, the thickness of the oxide layer 2 may increase.
As a result of the increase in the thickness of the oxide layer 2 as described above, the operation threshold voltage increases and the writing / erasing speed decreases.
Therefore, it can be seen that it is desirable to form the oxide layer 2 made of rare earth oxide by an appropriate method and conditions.

Therefore, in the memory element 10 of the present embodiment, the memory layer 5 (the oxide layer 2 and the ionized layer 3) among the layers constituting the memory element 10 is characterized by its formation method. .
That is, as the oxide layer 2, a copper oxide is formed in advance instead of the rare earth element oxide to be finally formed, and the ionized layer 3 containing the rare earth element is formed thereon.
Thereafter, by performing a heat treatment step, copper is diffused from the oxide layer 2 to the ionized layer 3 and a rare earth element is diffused from the ionized layer 3 to the oxide layer 2.
Thereby, the oxide layer 2 made of a rare earth element oxide is formed.

  The heat treatment step is desirably performed at a temperature of 250 ° C. or higher in order to sufficiently diffuse copper and rare earth elements.

The oxide layer 2 to be formed in advance may be copper oxide or an oxide containing 50% or more of Cu.
As components other than Cu, among rare earth elements, one or more elements selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Y, Si, Ge Etc. are suitable.
In the case of copper oxide, a composition of CuO or Cu ₂ O is usually formed. However, the composition is not necessarily limited to such a composition, and may be a composition composed of Cu and O. For example, CuOx (0. 3 <x ≦ 1.2).

  Further, the thickness of the oxide layer 2 is reduced to, for example, a thickness of 0.5 nm to 3 nm so that a current can flow.

  As a specific method of forming the oxide layer 2 made of copper oxide, after forming a Cu metal film using a metal target, plasma oxidation in which oxygen is oxidized by oxygen plasma using oxygen alone or a mixed gas with Ar, A method of introducing oxygen or the like together with an inert gas such as argon during sputtering, so-called reactive sputtering, or the like can be used.

  The ionization layer 3 formed in advance may be a single layer or may be a stack of a plurality of layers having different main components. Moreover, you may assign rare earth elements, chalcogenide elements, and Cu to each of the plurality of layers.

That is, for example, the laminated film 6 whose sectional view is shown in FIG.
In the laminated film 6, the oxide layer 2 is made of copper oxide.
Further, the ionized layer 3 is formed by stacking a layer 3A containing a rare earth element, a layer 3B containing a chalcogenide element, and a layer 3C supplemented with Cu.
Then, by performing a heat treatment process on the laminated film 6, the copper Cu of the oxide layer 2 and the rare earth element of the layer 3A containing the rare earth element are diffused.
Thereby, the oxide layer 2 comprised from a rare earth oxide can be formed with the diffused rare earth element.
In this way, the memory element 10 having the configuration shown in FIG. 1 is formed.

  In fact, since the element is diffused by the heat treatment, the boundary between the oxide layer 2 and the ionized layer 3 is not as clear as that at the time of film formation. The layer 3 can be collectively regarded as the storage layer 5.

  Further, by causing the diffusion of the elements due to the heat treatment, the distribution of copper Cu and rare earth elements in the memory element 10 is different from the distribution in the laminated film 6 of FIG. The boundaries between the three layers 3A, 3B, and 3C are not as clear as the state of the laminated film 6 in FIG.

In the laminated film 6 of FIG. 4, the material of each layer 3A, 3B, 3C forming the ionized layer 3 can be, for example, as follows.
The layer 3A containing a rare earth element contains one or more elements selected from rare earth elements (La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Y). And Further, Cu may be contained in this layer 3A.
For the layer 3B containing the chalcogenide element, a compound of the chalcogenide element, for example, GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe can be used. The layer 3B may contain a rare earth element or Cu. For example, GeTeGd, CuGeTe, CuGeTeGd, or the like may be used.
The layer 3C for supplementing Cu is a layer formed to supplement Cu so that the ionized layer 3 contains sufficient Cu. Pure Cu or a Cu alloy such as CuSi, CuGe, CuGd, CuZr, etc. Can be used. When using a Cu alloy, the Cu content is desirably 30% or more, and other contained elements are not particularly limited.
In addition, you may add other elements, for example, B, P, and N, to each layer 3A, 3B, 3C.

The layer 3A containing a rare earth element preferably has a thickness of 5 nm or less.
The layer 3B containing a chalcogenide element preferably has a thickness of 5 nm to 50 nm.
The layer 3C for supplementing Cu preferably has a thickness of 1 to 50 nm.

The rare earth element contained in the ionized layer 3 is diffused into the oxide layer 2 by heat treatment to form a rare earth element oxide. Depending on the thickness and quality of the rare earth element oxide formed after the heat treatment, writing and Characteristic values such as the erase threshold voltage and operation speed are greatly affected.
Therefore, it is desirable to adjust so that rare earth elements are present as much as necessary to obtain optimum operating characteristics.

Therefore, when the laminated film 6 is formed, the amount of rare earth elements contained in the entire ionized layer 3 is adjusted.
In the layer 3A containing a rare earth element, the amount of the rare earth element can be adjusted by the content and thickness of the rare earth element.
When the other two layers 3B and 3C are also made to contain rare earth elements, the amount of rare earth elements contained in the entire ionized layer 3 is adjusted to the required amount together with the rare earth element containing layer 3A. .

Not only the structure of the laminated film 6 shown in FIG. 4 but various structures are possible for the layer formed to form the ionized layer 3.
Several other forms of the laminated film for manufacturing the memory element 10 of FIG. 1 will be described below.

In the laminated film 7 shown in a sectional view in FIG. 5, the ionized layer 3 is formed by laminating a layer 3B containing a chalcogenide element and a layer 3C supplementing Cu.
When this laminated film 7 is used, the rare earth element is contained in the layer 3B containing the chalcogenide element.
The layer 3B containing the chalcogenide element may contain Cu, or the layer 3C supplemented with Cu may contain a rare earth element.

  In the laminated film 7, the chalcogenide element-containing layer 3B has a composition in which a rare earth element is added in an amount of about 0 to 10% with respect to GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, or the like. An alloy film is formed.

  In the laminated film 7, the amount of the rare earth element can be adjusted mainly by the content and film thickness of the rare earth element of the layer 3B containing the chalcogenide element.

In the laminated film 8 shown in a sectional view in FIG. 6, the ionized layer 3 is formed by laminating a layer 3A containing a rare earth element and a layer 3B containing a chalcogenide element.
When the laminated film 8 is used, Cu is contained in at least one of the layer 3B containing the chalcogenide element or the layer 3A containing the rare earth element.
The layer 3B containing a chalcogenide element may also contain a rare earth element.

  In this laminated film 8, the amount of rare earth elements can be adjusted in substantially the same manner as in the laminated film 6 shown in FIG.

In the laminated film 9 having a cross-sectional view shown in FIG. 7, the ionized layer 3 is formed only by the layer 3B containing the chalcogenide element.
When this laminated film 9 is used, the rare earth element and Cu are contained in the layer 3B containing the chalcogenide element.

  In the laminated film 9, the amount of the rare earth element can be adjusted by the rare earth element content and the film thickness of the layer 3B containing the chalcogenide element.

  Whichever of the above laminated films 6, 7, 8, 9 is used, the oxide layer 2 made of rare earth element oxide can be formed by the heat treatment process.

In addition, when the rare earth element is not contained in the layer 3B containing the chalcogenide element, the layer 3A containing the rare earth element is necessary.
Further, when Cu is not contained in the layer 3B containing the chalcogenide element, the layer 3C for supplementing Cu is required. Even when the sum of the Cu contents of the other layers 3A and 3B is not sufficient, the layer 3C for supplementing Cu is required.
As a rough guideline, the Cu content of the two layers 3A, 3B or the Cu content of the respective layers 3A, 3B, 3C forming the ionized layer 3 so that the total amount of Cu is 30% or more by atomic composition ratio, The presence / absence of the layer 3C that compensates for this may be set.

  Next, the diffusion mechanism of elements in the oxide layer 2 and the ionized layer 3 in the heat treatment step described above will be described with reference to the schematic diagrams of FIGS. 8A to 8D.

  First, in the state in which the laminated films 6, 7, 8, and 9 constituting the memory element 10 are formed, the oxide layer 2 has copper oxide (Cu—O) as shown in FIG. 3 includes rare earth elements (RE).

When heat treatment is applied here, first, as shown in FIG. 8B, copper (Cu) is liberated from the copper oxide of the oxide layer 2, and copper (Cu) diffuses toward the ionized layer 3 as indicated by an arrow. At the same time, the rare earth element (RE) in the ionized layer 3 tends to diffuse toward the oxide layer 2 as indicated by the arrow.
Further, the copper (Cu) and the rare earth element (RE) are diffused by the heat treatment, so that the copper (Cu) enters the ionization layer 3 and the rare earth element (RE) becomes the oxide layer 2 as shown in FIG. 8C. to go into. Oxygen (O) remains in the oxide layer 2.

  Then, as shown in FIG. 8D, the rare earth element (RE) entering the oxide layer 2 is combined with oxygen (O) to form a rare earth element oxide (RE-O). As a result, the main component of the oxide layer 2 is changed to a rare earth element oxide.

8C and 8D, a part of copper (Cu) may remain in the oxide layer 2, and the oxide layer 2 of the memory element 10 may contain copper.
Although there is a difference in the diffusibility between copper and rare earth elements, the ionization layer 3 contains copper (not shown) (particularly 3C or 3B). This is also because the amount of) is greater than that of rare earth elements (RE).
Although not shown, a part of the rare earth element may remain in the ionization layer 3 and the ionization layer 3 of the memory element 10 may contain the rare earth element.

  Specifically, the memory element 10 of the present embodiment can be manufactured as follows, for example. In this specific example, the laminated film 7 shown in FIG. 5 is formed.

First, a lower electrode 1 made of, for example, W is formed on a substrate on which a CMOS circuit such as a selection transistor is formed.
Thereafter, if necessary, oxides on the surface of the lower electrode 1 are removed by reverse sputtering or the like.

Next, an oxide layer 2 made of a Cu oxide film is formed. For example, after forming a metal Cu film with a film thickness of, for example, 1 nm using a Cu target, the film is oxidized by oxygen plasma.
Next, as a layer 3B containing a chalcogenide element for forming the ionized layer 3, for example, a GeTeGd film is formed by DC magnetron sputtering.
Further, for example, a Cu film is formed as the layer 3C for supplementing Cu for forming the ionized layer 3.
Next, for example, a W film is formed as the upper electrode 4.
Thereby, the laminated film 7 shown in FIG. 5 is formed.

Thereafter, the oxide layer 2, the ionized layers 3 (3B, 3C), and the upper electrode 4 among the layers of the laminated film 7 are patterned by plasma etching or the like. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
Next, by forming a wiring layer connected to the upper electrode 4, the memory element 10 and a contact for obtaining a common potential are connected.

Next, a heat treatment process is performed on the laminated film 7. Accordingly, Gd oxide is formed in the oxide layer 2 by diffusing Gd from the layer 3B containing the chalcogenide element into the oxide layer 2.
In this way, the memory element 10 can be manufactured.

According to the above-described embodiment, the oxide layer 2 made of copper oxide is formed, and the ionized layer 3 containing the rare earth element, Cu, and chalcogenide element is formed, and the oxide layer 2 and the ionized layer are formed. 3 are formed, and Cu is diffused from the oxide layer 2 to the ionized layer 3 and a rare earth element is diffused from the ionized layer 3 to the oxide layer 2 by a subsequent heat treatment step. By diffusion, a rare earth element oxide is formed in the oxide layer 2 to form the memory layer 5 (2, 3) of the memory element 10.
Thereby, the oxide layer 2 having a necessary thickness and thermally stable can be formed by diffusion of rare earth elements.
Since the thickness and the like of the oxide layer 2 made of the rare earth element oxide can be easily controlled by controlling the content of the rare earth element in the ionized layer 3, the memory element 10 has desirable operating characteristics. It can control to have.
In addition, since the oxide layer 2 made of a rare earth element oxide is thermally stable, it is possible to suppress changes in operating characteristics when receiving heat during manufacturing.

Accordingly, it is possible to reduce non-uniformity of the oxide layer 2 and suppress variation in threshold voltage in writing and erasing of the memory element 10, thereby reducing occurrence of errors in writing and erasing information. In addition, the memory element 10 having excellent repetitive characteristics of writing and erasing operations can be obtained.
Since it is possible to reduce the occurrence of errors in writing and erasing information in the memory element 10, it is possible to realize a memory device including a large number of memory elements 10 and capable of stable memory operation.
By making the memory element 10 excellent in the repetitive characteristics of writing and erasing operations, a memory device having a large number of memory elements 10, excellent in durability of information retention, and having high reliability can be obtained. Can be realized.

  Further, since the threshold voltage in writing and erasing of the memory element 10 can be suppressed to be low, writing and erasing can be performed on the memory element 10 in a short time (high speed). It is possible to realize a storage device having a large number of 10 and operating at high speed.

The memory element 10 according to the present embodiment can easily record and read information, and particularly has excellent characteristics such that variations in threshold voltages for writing and erasing are small.
Further, even when the memory element 10 of the present embodiment is miniaturized, it becomes easy to record information and hold recorded information.
Therefore, by configuring the memory device using the memory element 10 of this embodiment, the memory device can be integrated (high density) or downsized.

Further, according to the memory element 10 of the present embodiment, the lower electrode 1, the oxide layer 2, the layers 3A, 3B, 3C that become the ionized layer 3, and the upper electrode 4 are all made of a material that can be sputtered. It is possible. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

  In the above-described embodiment, the oxide layer 2 is formed on the lower electrode 1 and the layers 3A, 3B, 3C of the ionization layer 3 and the upper electrode 4 are sequentially laminated. A Cu filling layer 3C containing Cu is formed thereon, then a layer 3B containing a chalcogenide element (Te, Se, S), then a layer 3A containing a rare earth element, and further an oxide layer 2 obtained by oxidizing Cu. As the laminated structure formed in order, the upper electrode layer 4 may be formed on the laminated structure, and the structure of the laminated order may be completely reversed.

In this way, even in the reverse stacking order, the layer 3B containing the chalcogenide element may contain Cu or a rare earth element. Further, when the layer 3B containing the chalcogenide element contains a necessary amount of Cu in advance, the layer 3C for supplementing Cu can be omitted.
Further, when the layer 3B containing the chalcogenide element does not contain the rare earth element, the layer 3A containing the rare earth element is formed between the oxide layer 2 and the layer 3B containing the chalcogenide element.
Furthermore, even in the reverse stacking order, elements such as B, N, and P can be added to the layers 3A, 3B, and 3C forming the ionized layer 3.

  Next, the memory element 10 and the memory cell array of the above-described embodiment were actually manufactured, and the characteristics were examined.

Example 1
First, as shown in FIGS. 2 and 3, a MOS transistor Tr was formed on the semiconductor substrate 11.
Thereafter, an insulating layer was formed covering the surface.
Next, a via hole was formed in this insulating layer.
Subsequently, the via hole was filled with an electrode material made of WN (tungsten nitride) by CVD.
Next, the surface was planarized by CMP.
Then, by repeating these steps, the plug layer 15, the metal wiring layer 16, the plug layer 17, and the lower electrode 1 were formed, and the lower electrode 1 was further patterned for each memory cell.

Next, in order to remove the lower electrode 1 formed on the semiconductor substrate 11 on which the CMOS circuit including the MOS transistor Tr is formed, that is, the oxide on the upper surface of the tungsten nitride plug (WN plug), reverse using an RF power supply is performed. Etching was about 1 nm by sputtering.
At this time, it is desirable that the surface of the lower electrode 1 is ideally formed at the same height as the surrounding insulating layer and is flattened.

Next, a metal Cu film having a film thickness of 1.0 nm is formed by DC magnetron sputtering, and the Cu film is further oxidized for 120 seconds by RF plasma with O ₂ : Ar = 1: 3, chamber pressure 1 mTorr, and input power 500 W. Cu oxide was formed to form an oxide layer 2.

Next, as a layer 3A containing a rare earth element, a Gd film is deposited by 1 nm, as a layer 3B containing a chalcogenide element, a GeTeGd film is deposited by 20 nm, and then a Cu film is deposited by 20 nm as a layer 3C to supplement Cu. did. The ionized layer 3 was formed by stacking these layers 3A, 3B, and 3C.
Further, a W film having a film thickness of 20 nm was formed on the ionized layer 3 as the upper electrode 4.
In this way, the laminated films 1, 2, 3 (3A, 3B, 3C), 4 constituting the memory element 10 shown in FIG. 1 were formed.

After that, the oxide layer 2, the ionized layer 3, and the upper electrode 4 formed on the entire surface are patterned so as to remain over the entire memory cell array portion (memory portion), thereby providing an external circuit for applying an intermediate potential (Vdd / 2). Etching was performed on the surface of the upper electrode 4 so that the contact portion to be connected was exposed.
Furthermore, an Al layer serving as a wiring was formed with a thickness of 200 nm so as to be connected to the exposed contact portion.

Subsequently, heat treatment was performed at 265 ° C. for 4 hours in a vacuum heat treatment furnace.
In this way, a memory cell array composed of the memory elements 10 shown in FIGS. 1 to 3 was produced and used as a sample of Example 1.

(Example 2)
As a layer 3B containing a chalcogenide element, a GeTeGd film was deposited with a thickness of 20 nm, and as a layer 3C supplemented with Cu, a Cu film was deposited with a thickness of 20 nm. The ionized layer 3 was formed by laminating these layers 3B and 3C.
Other than that, a memory cell array composed of memory elements was produced in the same manner as in Example 1 and used as a sample of Example 2. In Example 2, the laminated film 7 having the configuration shown in FIG. 5 is used.

(Example 3 and Example 4)
A memory cell array composed of memory elements was prepared in the same manner as in Example 1 except that the thickness of the Gd film of the layer 3A containing rare earth elements was 0.5 nm and 2 nm, respectively. Four samples were obtained.

(Example 5)
A memory cell array composed of memory elements was fabricated in the same manner as in Example 1 except that the thickness of the Gd film of the layer 3A containing the rare earth element was 2 nm and the GeTe film was deposited as the layer 3B containing the chalcogenide element by 20 nm. Thus, a sample of Example 5 was obtained.

(Example 6)
As the layer 3A containing a rare earth element, a Gd film was deposited to 1 nm, and as the layer 3B containing a chalcogenide element, a CuGeTeGd film was deposited to 20 nm. The ionized layer 3 was formed by laminating these layers 3A and 3B.
Other than that, a memory cell array composed of memory elements was fabricated in the same manner as in Example 1, and a sample of Example 6 was obtained. In Example 6, the laminated film 8 having the configuration shown in FIG. 6 is used.

(Comparative Example 1)
The surface of the lower electrode 1 was etched by about 5 nm by reverse sputtering using an RF power source.
Thereafter, a metal Gd film having a thickness of 0.6 nm was formed. Further, the Gd oxide was formed by oxidizing the Gd film by exposure to oxygen plasma, whereby the oxide layer 2 was obtained.
Next, a GeTeGd film having a thickness of 20 nm was deposited as a layer 3B containing a chalcogenide element, and then a Cu film having a thickness of 20 nm was deposited as a layer 3C for supplementing Cu. The ionized layer 3 was formed by laminating these layers 3B and 3C.
Other than that, a memory cell array composed of memory elements was produced in the same manner as in Example 1 and used as a sample of Comparative Example 1.

(Characteristic evaluation)
For example, with respect to the memory element 10 of the sample of the first embodiment, the upper wiring connected to the upper electrode 4 is grounded to an intermediate potential of Vdd / 2, and 2.5 V is applied to the gate electrode of the selected memory cell, that is, the word line WL. To the electrode connected to the one not connected to the memory element 10 among the source / drain 13 of the transistor Tr, that is, the bit line BL, 0V to + 2.25V, + 2.25V to A voltage of −1.5 V and −1.5 V to 0 V was applied for insertion, and these cycles were repeated twice in total.

FIG. 9A shows the IV characteristics of the memory element of the sample of Example 1 obtained as described above.
Further, the VR loop was calculated from the IV characteristics. The calculated VR loop is shown in FIG. 9B.
9A and 9B, the broken line indicates the first loop, and the solid line indicates the second and subsequent loops.

From FIG. 9A and FIG. 9B, the resistance value is high in the initial stage immediately after the device fabrication, the memory device is in the OFF state, the voltage is applied to the bit line, and the voltage of the lower electrode of the device increases negatively with respect to the upper electrode. By doing this (in the positive direction in the figure), the current abruptly increases above the threshold voltage (Vth) of 0.7 to 1.4V. That is, it can be seen that the resistance value of the memory element is lowered and the memory element shifts to the ON state. Thereby, information is recorded.
On the other hand, even if the voltage is decreased thereafter, the constant resistance value is maintained, that is, the storage element is kept in the ON state, and the recorded information is retained. Further, the same operation is performed even if the subsequent record erasure is performed.

  Also, as shown in the figure, when a reverse polarity voltage V, that is, a positive potential (+ potential) is applied to the lower electrode, a positive potential of V = −0.7 V or more is applied, and then it is returned to 0 V again. Thus, it was confirmed that the resistance value of the memory element returned to the high resistance state in the initial OFF state. That is, it can be seen that the information recorded in the memory element can be erased by applying a negative voltage.

Next, for each sample of Example 1 and Comparative Example 1, in order to evaluate the writing characteristics, the gate voltage is 2.5 V, the element voltage including the MOS transistor is 2.5 V, and the pulse width is 1 ns to 1 ms. The resistance value after writing with a pulse voltage was measured for each of 20 memory elements.
As measurement results, 20 measured values of each pulse width are plotted and shown in FIGS. 10A and 10B. FIG. 10A shows the measurement result of the sample of Comparative Example 1, and FIG. 10B shows the measurement result of the sample of Example 1.

From FIG. 10A, in the sample of Comparative Example 1 in which the oxide layer 2 made of Gd oxide was directly formed, writing failure started to occur from 1 μs.
On the other hand, from FIG. 10B, in the sample of Example 1 in which the oxide layer 2 made of Cu oxide and the ionized layer 3 containing Gd were formed, and the oxide layer 2 made of Gd oxide was formed by heat treatment, the sample of Example 1 No write failure has occurred.
Therefore, it can be seen that the writing speed characteristic is improved in Example 1 as compared with Comparative Example 1.

Subsequently, the stability of writing and erasing was examined for each sample.
First, a reference value was obtained in order to quantify writing and erasing defects. That is, when writing and erasing are performed with a relatively long pulse width of 1 ms, each resistance value after writing and after erasing is measured with 20 memory elements, and the logarithm of the measured resistance value is taken and an average of them is taken. The value was calculated. Further, an intermediate value was obtained from each average value after writing and after erasing, and used as a reference value.
Next, writing and erasing were performed with a pulse width of 100 ns. Similarly, each resistance value after writing and after erasing was measured with 20 memory elements, and the logarithm of the measured resistance value was taken.
Then, it was compared with the previously obtained reference value, that is, the intermediate value of each average value after writing and erasing (in the case of a pulse width of 1 ms). In the case of writing, a memory element that exceeded the intermediate value and did not decrease the resistance value was regarded as defective. In the case of erasing, a memory element having a resistance value lower than the intermediate value and not fully increased was regarded as defective. Of the 20 measured memory elements, the proportion of defective elements was examined for each sample of Examples 1 to 6 and Comparative Example 1.
Table 1 shows the write and erase defect rates as measurement results.

From Table 1, no writing error was found in Examples 1 to 6, but in Comparative Example 1, there was 20% writing error.
Further, the erasure error is 20% in Comparative Example 1, while the samples of Examples 1 to 6 in which the oxide layer is formed by heat treatment from the Cu oxide layer are all suppressed to 10% or less. It has been.

  Therefore, since the samples of each example can be written and erased with a short pulse width, the speed characteristics of the writing / erasing operation are excellent, and it can be said that the writing characteristics and the erasing characteristics are balanced. .

The cause of this is not necessarily clear, but is probably due to the change described by FIGS. 8A to 8D.
That is, when the heat treatment is performed after forming the oxide layer 2 with Cu oxide, Gd in the ionized layer 3 diffuses to the oxide layer 2 side during the heat treatment, and the Gd oxide is contained in the oxide layer 2. This is considered to be because a necessary and sufficient and uniform oxide film is formed.

A memory device (memory device) can be configured by arranging a large number of memory elements, for example, in a column or matrix, using the memory elements of the present invention as shown in the above-described embodiments and the like. .
At this time, a memory cell is configured by connecting a MOS transistor or a diode for selecting the element to each memory element as necessary.
Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. It is possible to apply any memory form such as (memory).

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element of the present invention. It is a schematic block diagram (sectional drawing) of the memory cell array using the memory element of FIG. FIG. 2 is a schematic configuration diagram (plan view) of a memory cell array using the memory element of FIG. 1. It is sectional drawing of one form of the laminated film formed when manufacturing the memory element of FIG. It is sectional drawing of the other form of the laminated film formed when manufacturing the memory element of FIG. It is sectional drawing of the other form of the laminated film formed when manufacturing the memory element of FIG. It is sectional drawing of the other form of the laminated film formed when manufacturing the memory element of FIG. AD is a figure explaining the change mechanism by the heat processing at the time of manufacture in the memory element of this invention. A It is a measurement result of the IV characteristic curve of the sample of Example 1. FIG. B is a measurement result of the VR loop of the sample of Example 1. This is a result of measuring the resistance value by changing the pulse width of the write pulse. A is a measurement result of the sample of Comparative Example 1. B is a measurement result of the sample of Example 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Oxide layer, 3 Ionization layer, 4 Upper electrode, 5 Memory layer, 6, 7, 8, 9 Laminated film, 10 Memory element, Tr MOS transistor, BL bit line, WL word line, PL plate electrode

Claims (12)

A memory layer is sandwiched between the first electrode and the second electrode,
The memory layer is formed by stacking an oxide layer and an ionized layer containing Cu to be ionized,
The oxide layer comprises a rare earth element oxide;
The ionization layer contains one or more elements selected from S, Se, and Te.   The memory element according to claim 1, wherein the oxide layer contains Cu.   The memory element according to claim 1, wherein the ionized layer contains a rare earth element.   2. The memory element according to claim 1, wherein the rare earth element of the rare earth element oxide is diffused from the ionized layer to the oxide layer.   2. The storage element according to claim 1, wherein information is recorded by changing the impedance of the storage layer by applying a voltage pulse or a current pulse to the storage layer. A method for manufacturing a memory element having a memory layer sandwiched between a first electrode and a second electrode,
A step of forming an oxide layer made of copper oxide, and a step of forming an ionized layer containing a rare earth element and at least one element selected from Cu, S, Se, and Te, and the oxide layer and Forming a laminated film in which the ionized layers are laminated;
Thereafter, a heat treatment step diffuses Cu from the oxide layer to the ionized layer, and diffuses the rare earth element from the ionized layer to the oxide layer, thereby forming a rare earth element oxide in the oxide layer. Then, the memory layer constituted by the oxide layer and the ionized layer is manufactured.   In the step of forming the ionized layer, a layer containing a rare earth element, a layer containing one or more elements selected from S, Se, and Te, and a layer containing Cu are laminated to form the ionized layer. The method of manufacturing a memory element according to claim 6, wherein: is formed.   In the step of forming the ionized layer, a layer containing a rare earth element and a layer containing one or more elements selected from S, Se, and Te are stacked, and Cu is contained in at least one of the two layers. The method of manufacturing a memory element according to claim 6, wherein the ionized layer is formed.   In the step of forming the ionized layer, a layer containing one or more elements selected from S, Se, and Te and a layer containing Cu are laminated, and at least one of the two layers contains a rare earth element. The method of manufacturing a memory element according to claim 6, wherein the ionized layer is formed.   The method for manufacturing a memory element according to claim 6, wherein the heat treatment step is performed at a temperature of 250 ° C. or higher. A memory layer is sandwiched between the first electrode and the second electrode, and the memory layer is formed by stacking an oxide layer and an ionized layer containing Cu to be ionized, and the oxide A layer made of a rare earth element oxide, and the ionized layer containing one or more elements selected from S, Se, Te;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device comprising a large number of the storage elements.   The memory device according to claim 11, wherein in a plurality of adjacent memory elements, at least a part of layers constituting the memory element is formed in common by the same layer.

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