JP4810957B2 - ハイブリットモジュール及びその製造方法 - Google Patents

ハイブリットモジュール及びその製造方法 Download PDF

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Publication number
JP4810957B2
JP4810957B2 JP2005296734A JP2005296734A JP4810957B2 JP 4810957 B2 JP4810957 B2 JP 4810957B2 JP 2005296734 A JP2005296734 A JP 2005296734A JP 2005296734 A JP2005296734 A JP 2005296734A JP 4810957 B2 JP4810957 B2 JP 4810957B2
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JP
Japan
Prior art keywords
silicon substrate
layer
mounting
component
hybrid module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005296734A
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English (en)
Japanese (ja)
Other versions
JP2006270036A5 (https=
JP2006270036A (ja
Inventor
剛 小川
浩和 中山
廣仁 宮崎
奈美子 竹島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2005296734A priority Critical patent/JP4810957B2/ja
Priority to US11/528,965 priority patent/US20070080458A1/en
Publication of JP2006270036A publication Critical patent/JP2006270036A/ja
Priority to CN2006101411105A priority patent/CN1949506B/zh
Priority to KR1020060098287A priority patent/KR20070040305A/ko
Priority to US12/077,486 priority patent/US7915076B2/en
Publication of JP2006270036A5 publication Critical patent/JP2006270036A5/ja
Application granted granted Critical
Publication of JP4810957B2 publication Critical patent/JP4810957B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)
JP2005296734A 2005-02-28 2005-10-11 ハイブリットモジュール及びその製造方法 Expired - Fee Related JP4810957B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2005296734A JP4810957B2 (ja) 2005-02-28 2005-10-11 ハイブリットモジュール及びその製造方法
US11/528,965 US20070080458A1 (en) 2005-10-11 2006-09-27 Hybrid module and method of manufacturing the same
CN2006101411105A CN1949506B (zh) 2005-10-11 2006-10-09 混合模块和其制造方法
KR1020060098287A KR20070040305A (ko) 2005-10-11 2006-10-10 하이브리드 모듈 및 그 제조 방법
US12/077,486 US7915076B2 (en) 2005-10-11 2008-03-19 Hybrid module and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005054848 2005-02-28
JP2005054848 2005-02-28
JP2005296734A JP4810957B2 (ja) 2005-02-28 2005-10-11 ハイブリットモジュール及びその製造方法

Publications (3)

Publication Number Publication Date
JP2006270036A JP2006270036A (ja) 2006-10-05
JP2006270036A5 JP2006270036A5 (https=) 2008-11-27
JP4810957B2 true JP4810957B2 (ja) 2011-11-09

Family

ID=37205613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005296734A Expired - Fee Related JP4810957B2 (ja) 2005-02-28 2005-10-11 ハイブリットモジュール及びその製造方法

Country Status (1)

Country Link
JP (1) JP4810957B2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2917233B1 (fr) * 2007-06-07 2009-11-06 Commissariat Energie Atomique Integration 3d de composants verticaux dans des substrats reconstitues.
FR2917234B1 (fr) * 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
US8736065B2 (en) * 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
JP6561602B2 (ja) * 2015-06-09 2019-08-21 富士通株式会社 電子装置の製造方法
CN115298589B (zh) * 2020-03-19 2026-03-20 日东电工株式会社 光电传输复合模块
JPWO2022030001A1 (https=) * 2020-08-07 2022-02-10
JP2022115723A (ja) * 2021-01-28 2022-08-09 アイオーコア株式会社 光電気モジュール
WO2023195236A1 (ja) * 2022-04-08 2023-10-12 ソニーセミコンダクタソリューションズ株式会社 パッケージおよびパッケージの製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630096A (en) * 1984-05-30 1986-12-16 Motorola, Inc. High density IC module assembly
FR2667443A1 (fr) * 1990-09-28 1992-04-03 Thomson Csf Procede de realisation d'un module hybride.
JP3819483B2 (ja) * 1996-07-17 2006-09-06 三洋電機株式会社 半導体装置
JP2004079736A (ja) * 2002-08-15 2004-03-11 Sony Corp チップ内蔵基板装置及びその製造方法
JP4042555B2 (ja) * 2002-12-09 2008-02-06 ソニー株式会社 半導体回路素子・光学素子混載ハイブリットモジュール及びその製造方法
EP1487019A1 (en) * 2003-06-12 2004-12-15 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing thereof

Also Published As

Publication number Publication date
JP2006270036A (ja) 2006-10-05

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